Abstract: A manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.

Abstract: A silicon carbide semiconductor device has an active area, a termination area surrounding the active area in a plan view. The silicon carbide semiconductor device comprises a SiC substrate, a drift layer, an insulating layer, a polysilicon layer, an interlayer dielectric layer disposed on the polysilicon layer, and a metal layer. The polysilicon layer includes a first portion disposed over the active area and a second portion disposed over the termination area. The metal layer includes a first portion disposed over the active area and a second portion disposed over the termination area. At least one of the second portion of the polysilicon layer and the second portion of the metal layer is configurated to electrically connect to at least one of a gate electrode and a source electrode.

Abstract: A capacitor device connected to a semiconductor device includes a capacitor element including a first electrode and a second electrode, a first wiring and a second wiring. The first wiring has a first one end portion connected to the first electrode and a first other end portion connected to a first electrode terminal of the semiconductor device, and the second wiring has a second one end portion connected to the second electrode and a second other end portion connected to a second electrode terminal of the semiconductor device. A resistor is provided between the first one end portion and the first other end portion of the first wiring and is electrically connected directly to the first wiring.

Abstract: A semiconductor light emitting device includes a board including a first principal surface facing a first side in a thickness direction thereof, a first electrode provided on the board, a semiconductor light emitting element, and a light-transmitting resin that covers the element. The first electrode includes a first bonding portion and first, second, and third portions. The first bonding portion is formed on the first principal surface and is joined and electrically connected to the element. The first and second portions are each formed on the first principal surface and disposed on a first side in a first direction. The first portion is connected to the first bonding portion. The second portion is apart from the first bonding portion, and from the first portion in a second direction. The third portion is formed on a place different from the first principal surface, electrically connecting the first and second portions to each other.

Abstract: Provided are a display panel and a display apparatus. The display panel includes a base substrate, the base substrate includes a display region and a non-display region surrounding the display region, and the non-display region includes a first bezel region and a second bezel region having a binding region; blocking dams located in the non-display region and arranged surrounding the display region, the blocking dams include a first blocking dam and a second blocking dam, and the first blocking dam is located between the second blocking dam and the display region; and a first flat layer, a second flat layer and a third flat layer located on the base substrate; the second blocking dam includes the first flat layer and the third flat layer in the first bezel region, and the second blocking dam includes the second flat layer and the third flat layer in the second bezel region.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes receiving a structure comprising a metal feature, a first passivation structure over the metal feature, and a first opening extending through the first passivation structure and exposing the metal feature. The exemplary method also includes forming a conductive layer in the first opening; forming a second passivation structure over the conductive layer, performing a first etching process to form a second opening extending through the second passivation structure and exposing the conductive layer, performing a second etching process to selectively remove an upper portion of the second passivation structure to enlarge an upper portion of the second opening, and after the performing of the second etching process, forming a conductive feature in the second opening.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes an S/D contact structure formed over the first S/D structure, and a dielectric wall formed below the gate structure and the S/D contact structure. The dielectric wall has a first portion directly below the S/D contact structure and a second portion directly below the gate structure, the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height.

Abstract: A p-n junction based III-nitride device in which the p-type layers adjacent to the n-type layers are activated by thermal annealing with a porous n-type tunnel junction layer or layers. The porosity of the n-type tunnel junction layer(s) allows for gas exchange to occur, allowing efficient p-type nitride semiconductor activation. This porosification and activation step can be inserted wherever desired into an existing fabrication process for an LED, laser diode, or any other nitride semiconductor device. In one example, the device comprises multiple LED structures grown successively, separated by tunnel junctions and the buried p-type layers are activated by thermal annealing with adjacent porous n-type layers. Using this method, efficient monolithic multi-color LEDs can be formed.

Abstract: The present disclosure discloses a manufacturing method including forming a stack including a first insulating layer, and a first sacrificial layer and a second insulating layer which are sequentially stacked on the first insulating layer; forming a patterned stack including at least one pattern portion having a first sacrificial layer obtained from the first sacrificial layer by patterning the stack; forming a structure including the patterned stack and the insulating material by filling empty spaces on both sides of the at least one pattern portion with an insulating material; forming a first vertical hole penetrating through the first sacrificial layer pattern of the pattern portion in the structure; forming a horizontal hole by removing the first sacrificial layer pattern exposed by the first vertical hole; and forming a gate insulating material layer on inner surfaces of the first vertical hole and the horizontal hole.

Abstract: A module includes: a substrate having a first surface; a first component mounted on the first surface; a first sealing resin that seals at least a part of the first surface and at least a side surface of the first component; and a shield film that is grounded and covers a surface of the first sealing resin on a side farther from the substrate. A surface of the first component on a side farther from the substrate is exposed from the first sealing resin. When the surface of the first component that is exposed from the first sealing resin is defined as a first exposed surface, the first exposed surface has a region covered with the shield film, the region including a strip-shaped portion that is locally reduced in surface roughness.

Abstract: A method for forming a structure with a backside power delivery network incorporates a high thermal conductivity material as the bonding layer. In some embodiments, the method may comprise forming a first layer stack that includes a front side metallization (FSM) signal layer formed on a silicon die layer containing nano-through silicon vias (n-TSVs) that is formed on a back side metallization (BSM) power distribution layer where the n-TSVs provide back side power connections to the FSM signal layer, forming a second layer stack that includes a silicon carrier layer, and forming a third layer stack that includes the first layer stack and the second layer stack bonded together with a bonding layer interposed between the first layer stack and the second layer stack where the bonding layer is formed of a cubic-boron nitride-based material.

Abstract: An image sensor comprises a substrate that comprises a first surface, a second surface facing the first surface, and a plurality of pixel regions disposed along a first direction and a second direction. The sensor comprises a plurality of ground regions that are disposed within a portion of the substrate along a depth direction perpendicular to the first direction and the second direction from the first surface of the substrate. The sensor comprises a deep trench that extends from the first surface of the substrate to the second surface of the substrate. The sensor comprises a shallow trench that extends into the portion of the substrate along the depth direction from the first surface of the substrate and is disposed at an outer edge of at least a portion of the deep trench.

Abstract: A semiconductor structure includes alternating stacks of insulating layers and electrically conductive layers which are located over a substrate and are laterally spaced apart from each other by first backside trenches and second backside trenches that are interlaced along a horizontal direction, first backside trench fill structures located in the first backside trenches, and second backside trench fill structures located in the second backside trenches. Each of the first backside trench fill structures includes a respective set of first backside support bridge structures located at a first vertical spacing from the substrate, and each of the second backside trench fill structures includes a respective set of second backside support bridge structures located at a second vertical spacing from the substrate that is different from the first vertical spacing.

Abstract: A display device includes a first electrode and a second electrode on a base layer; a first insulating layer on the first electrode and the second electrode; a bank on the first insulating layer; a light emitting element in an area surrounded by the bank; and a second insulating layer on the bank. The second insulating layer forms an opening exposing a surface of the bank.

Abstract: Embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. The first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.

Abstract: A display device includes a bank disposed on a substrate, the bank surrounding at least a portion of each of a first emission area and a second emission area in a plan view; first alignment electrodes, at least a number of the first alignment electrodes being disposed in the first emission area; second alignment electrodes, at least a number of the second alignment electrodes being disposed in the second emission area; and a light emitting element disposed in each of the first emission area and the second emission area. An electrode most adjacent to the second emission area among the first alignment electrodes and an electrode most adjacent to the first emission area among the second alignment electrodes are spaced apart from each other with a dividing line disposed therebetween, and the dividing line overlaps the bank in a plan view.

Abstract: An electronic device including a substrate, a data line, a transparent conductive layer, a first light-shielding layer, and a second light-shielding layer is provided. The data line is disposed on the substrate. The transparent conductive layer is disposed on the data line and has a slit, wherein the slit has a trunk portion, and the trunk portion is extended in a first direction. The first light-shielding layer is disposed on the data line and overlapped with the data line. The second light-shielding layer is disposed on the first light-shielding layer. The first light-shielding layer is extended in a second direction, there is a first included angle between the first direction and the second direction, and the first included angle satisfies a following relationship: 0°??1?20°, wherein ?1 is the first included angle.

Abstract: The present application provides a substrate encapsulating method, a display panel, and a display device. The substrate encapsulating method includes providing a first underlay, and fabricating a switching device on the first underlay to form a switching substrate; providing a second underlay, and fabricating a light-emitting diode on the second underlay to form a light-emitting substrate; applying a frame glue to an edge of the switching substrate or an edge of the light-emitting substrate; and bonding the switching substrate and the light-emitting substrate with the frame glue to seal the light-emitting diode between the switching substrate and the light-emitting substrate.

Abstract: A vacuum packaging manufacturing method includes forming, on a silicon wafer, a lower layer including a first metal layer and a second metal layer formed on the first metal layer, forming anchor regions by etching parts of the second metal layer and depositing a dielectric layer on the second metal layer in which the anchor regions are formed, exposing a silicon oxide film by removing a partial region of the dielectric layer and removing silicon oxide inside the second metal layer covered by the dielectric layer through the removed partial region of the dielectric layer, and depositing an upper layer on the second metal layer and forming a third metal structure on the upper layer, wherein, as the upper layer is deposited on the second metal layer, a region from which the silicon oxide inside the second metal layer is removed is in a vacuum or subvacuum state.

Abstract: The invention relates to an LED package for UV light comprising an optoelectronic device which, in particular as a volume emitter, is designed to emit light in the ultraviolet spectrum during operation. The component is arranged on a carrier with two contact pads for electrical contacting. Furthermore, a frame surrounding the component and arranged on the carrier is provided with a gas-impermeable outlet region lying in a main radiation direction, so that a hermetically sealed cavity comprising an inner region of the carrier is formed, the side walls of the frame facing the optoelectronic device being bevelled and opening towards the main radiation direction. An ESD protection element arranged outside the inner area on the carrier is electrically connected to at least one of the two contact pads.