Patents Examined by Mark W Tornow
  • Patent number: 11942330
    Abstract: Exemplary methods of etching gallium oxide from a semiconductor substrate may include flowing a first reagent in a substrate processing region housing the semiconductor substrate. The first reagent may include HX. X may be at least one of fluorine, chlorine, and bromine. The semiconductor substrate may include an exposed region of gallium oxide. Fluorinating the exposed region of gallium oxide may form a gallium halide and H2O. The methods may include flowing a second reagent in the substrate processing region. The second reagent may be at least one of trimethylgallium, tin acetylacetonate, tetramethylsilane, and trimethyltin chloride. The second reagent may promote a ligand exchange where a methyl group may be transferred to the gallium halide to form a volatile Me2GaY or Me3Ga. Y may be at least one of fluorine, chlorine, and bromine from the second reagent. The methods may include recessing a surface of the gallium oxide.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: March 26, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Feng Q. Liu, Lisa J. Enman, Lakmal C. Kalutarage, Mark J. Saly
  • Patent number: 11943934
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within one or more stacked inter-level dielectric (ILD) layers over a substrate. An etch stop structure is disposed over the one or more lower interconnect layers and a bottom electrode is disposed over the etch stop structure. The bottom electrode electrically contacts the one or more lower interconnect layers. A magnetic tunnel junction (MTJ) stack is disposed over the bottom electrode. The MTJ stack has sidewalls arranged at a first angle with respect to a bottom surface of the MTJ stack. A top electrode is disposed over the MTJ stack. The top electrode has sidewalls arranged at a second angle with respect to a bottom surface of the top electrode. The second angle is greater than the first angle.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chern-Yow Hsu
  • Patent number: 11943972
    Abstract: The present disclosure provides a display panel and a manufacturing method thereof, which include a flexible substrate, an array layer, a pixel definition layer, an insulating layer, a light-emitting layer, an additional layer, and a first inorganic layer. The array layer, the pixel definition layer, and the insulating layer are sequentially disposed on the flexible substrate, the insulating layer includes first through holes and second through holes, the light-emitting layer is filled in the first through holes, and the additional layer is disposed on the pixel definition layer, in the second through holes, and on the insulating layer and the light-emitting layer. The first inorganic layer is disposed on the array layer and the additional layer.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: March 26, 2024
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Jiajia Sun
  • Patent number: 11935894
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Patent number: 11937481
    Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate and a white OLED display unit on the base substrate, and further includes: an optical adjustment structure on a light emitting side of the white OLED display unit, where the optical adjustment structure is in a peripheral region of each pixel region. The optical adjustment structure is configured to absorb light in a first wavelength range or convert light in a first wavelength range into light in a second wavelength range.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: March 19, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guang Yan, Changyen Wu, Linlin Wang, Yongqi Shen, Juanjuan You, Li Sun
  • Patent number: 11935907
    Abstract: Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 19, 2024
    Assignee: Adeia Semiconductor Technologies LLC
    Inventor: Rajesh Katkar
  • Patent number: 11937446
    Abstract: A display panel and a manufacture method thereof, and a display apparatus are provided. The display panel has a display region and a border region that surrounds the display region and includes a peripheral circuit region and a peripheral region; the peripheral circuit region is between the display region and the peripheral region. At least a part of a barrier structure of the display panel is in the peripheral circuit region, and the barrier structure includes an organic barrier layer including an opening passing through the organic barrier layer and an inorganic barrier layer covering the organic barrier layer and filling the opening; an extension direction of the opening is same as that of an edge, close to the opening, of the display panel the peripheral circuit is in the peripheral circuit region.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 19, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xinwei Gao, Kaihong Ma, Dacheng Zhang, Lang Liu, Chen Xu
  • Patent number: 11935984
    Abstract: A quantum dot including a core that includes a first semiconductor nanocrystal including zinc and selenium, and optionally sulfur and/or tellurium, and a shell that includes a second semiconductor nanocrystal including zinc, and at least one of sulfur or selenium is disclosed. The quantum dot has an average particle diameter of greater than or equal to about 13 nm, an emission peak wavelength in a range of about 440 nm to about 470 nm, and a full width at half maximum (FWHM) of an emission wavelength of less than about 25 nm. A method for preparing the quantum dot, a quantum dot-polymer composite including the quantum dot, and an electronic device including the quantum dot is also disclosed.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Seok Han, Sung Woo Kim, Jin A Kim, Tae Hyung Kim, Kun Su Park, Yuho Won, Jeong Hee Lee, Eun Joo Jang, Hyo Sook Jang
  • Patent number: 11929418
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 12, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Patent number: 11923399
    Abstract: A micro light-emitting diode display panel includes a substrate, at least one light-emitting element, a reflective layer and a light-absorbing layer. The at least one light-emitting element is disposed on the substrate to define at least one pixel, and each light-emitting element includes micro light-emitting diodes. The reflective layer is disposed on the substrate and located between the micro light-emitting diodes. The reflective layer has cavities surrounding the micro light-emitting diodes, such that a thickness of a portion of the reflective layer close to any one of the micro light-emitting diodes is greater than a thickness of a portion of the reflective layer away from the corresponding micro light-emitting diode. The light-absorbing layer is at least disposed in the cavities of the reflective layer.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 5, 2024
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Sheng-Yuan Sun, Loganathan Murugan, Po-Wei Chiu, Yun-Li Li
  • Patent number: 11923417
    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a substrate having a well, a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The base layer has an overlapping arrangement with the well. The structure further includes a dielectric layer positioned in a vertical direction between the first terminal and the substrate, the second terminal and the substrate, and the base layer and the substrate.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: March 5, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Hong Yu, Shesh Mani Pandey
  • Patent number: 11923482
    Abstract: A light emitting device and method of forming a light emitting device are disclosed. The light emitting device includes a light emitting diode and a phosphor layer formed on the light emitting diode, the phosphor layer including a plurality of phosphor particles formed in a particle layer, the particle layer including interstices between the phosphor particles, and a matrix material disposed in a portion of the interstices. A plurality of cavities may be disposed in a remaining portion of the interstices.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: March 5, 2024
    Assignee: Lumileds LLC
    Inventors: Joerg Feldmann, Marcel Rene Bohmer, Marinus Johannes Petrus Maria van Gerwen, Yu-Chen Shen
  • Patent number: 11916049
    Abstract: A LED light display having a plurality of LED bulb arrays and a louver panel defining a plurality of hole arrays. Each hole array can define openings that are sized and spaced to receive at least the distal end portions of the bulbs forming a single LED bulb array. The louver panel further has a plurality of shaped protrusions in the form of louvers that are configured to extend outwardly and forwardly from a front surface of the louver panel and are arranged in a plurality of columns and in a plurality of rows in regularly repeating patterns related to the pattern of the placement of a plurality of the plurality of hole arrays in the louver panel and are further configured to block at least a portion of the emission of light from the LED bulbs in both a horizontal and vertical direction.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: February 27, 2024
    Assignee: Formetco, Inc.
    Inventor: Jim Shimmin
  • Patent number: 11908979
    Abstract: A photocurable composition includes quantum dots, quantum dot precursor materials, a chelating agent, one or more monomers, and a photoinitiator. The quantum dots are selected to emit radiation in a first wavelength band in the visible light range in response to absorption of radiation in a second wavelength band in the UV or visible light range. The second wavelength band is different than the first wavelength band. The quantum dot precursor materials include metal atoms or metal ions corresponding to metal components present in the quantum dots. The chelating agent is configured to chelate the quantum dot precursor materials. The photoinitiator initiates polymerization of the one or more monomers in response to absorption of radiation in the second wavelength band.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yingdong Luo, Daihua Zhang, Hou T. Ng, Sivapackia Ganapathiappan, Nag B. Patibandla
  • Patent number: 11910596
    Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Alyssa N. Scarbrough, John D. Hopkins
  • Patent number: 11908847
    Abstract: An image display element includes micro light emitting elements disposed in an array on a driving circuit substrate. An excitation light emitting element includes a main body including a compound semiconductor, a metal electrode disposed on a side of the main body located closer to the driving circuit substrate, and a transparent electrode disposed on an opposite side to the driving circuit substrate, and a light emission layer included in the main body is disposed on a side opposite to the driving circuit substrate from a center portion of the main body.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 20, 2024
    Assignee: Sharp Fukuyama Laser Co., Ltd.
    Inventors: Katsuji Iguchi, Hidenori Kawanishi, Koji Takahashi, Hiroaki Onuma
  • Patent number: 11908977
    Abstract: A semiconductor light-emitting device includes a light-emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer which are sequentially stacked, a first insulating layer on the second semiconductor layer with a plurality of first openings having first widths and a plurality of second openings having second widths different from the first widths, a first electrode electrically connected to the first semiconductor layer through the first openings, a first sub-electrode layer between the second semiconductor layer and the first insulating layer, the first sub-electrode layer being exposed through the second openings, and a second sub-electrode layer on the first insulating layer, the second sub-electrode layer being connected to the first sub-electrode layer through the second openings, wherein a first distance between the first openings closest to each other is different from a second distance between the second openings closest to each other.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JungSung Kim, Junghee Kwak, Seong Seok Yang
  • Patent number: 11901481
    Abstract: An inventive light-emitting apparatus comprises an array of multiple light-emitting pixels, and one or more transmissive optical elements positioned at a light-emitting surface of the light-emitting pixel array. One or more of the light-emitting pixels is defective. Each optical element is positioned at a location of a corresponding defective light-emitting pixel, and extends over that defective pixel and laterally at least partly over one or more adjacent pixels. Each optical element transmits laterally at least a portion of light emitted by the adjacent pixels to propagate away from the array from the location of the defective pixel, reducing the appearance of the defective pixel.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: February 13, 2024
    Assignee: Lumileds LLC
    Inventors: Toni Lopez, Hossein Lotfi, Isaac Wildeson, Oleg Shchekin
  • Patent number: 11903263
    Abstract: A method of manufacturing a display device includes forming a first electrode on a substrate, forming a bank layer on the first electrode, wherein the bank layer includes an opening portion exposing at least a portion of the first electrode, forming a first bank layer and a second bank layer by baking the bank layer, wherein the second bank layer is on the first bank layer and has liquid repellency, forming a first layer on the first electrode, and forming a third bank layer and a fourth bank layer by baking the first bank layer and the second bank layer, wherein the fourth bank layer is on the third bank layer and has liquid repellency, wherein the fourth bank layer is thinner than the second bank layer.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 13, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dongha Lee, Jongjang Park, Seulgi Han
  • Patent number: 11891555
    Abstract: A phosphor having a favorable emission peak wavelength, narrow full width at half maximum, and/or high emission intensity is provided. Additionally, a light-emitting device, an illumination device, an image display device, and/or an indicator lamp for a vehicle having favorable color rendering, color reproducibility and/or favorable conversion efficiency are provided. The present invention relates to a phosphor including a crystal phase having a composition represented by a specific formula, and having a minimum reflectance of 20% or more in a specific wavelength region, in which the specific wavelength region is from the emission peak wavelength of the phosphor to 800 nm, and a light-emitting device comprising the phosphor.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: February 6, 2024
    Assignees: Mitsubishi Chemical Corporation, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Tomoyuki Kurushima, Yuhei Inata, Naoto Hirosaki