Patents Examined by Mark W Tornow
  • Patent number: 11145555
    Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, and forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins providing channels for the one or more vertical transport field-effect transistors. The method also includes forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack including a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer. The gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, ChoongHyun Lee, Hemanth Jagannathan
  • Patent number: 11145675
    Abstract: A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventors: Yung Jun Kim, Won Hyo Cha, Byung Soo Park, Sang Tae Ahn, Sung Jae Chung
  • Patent number: 11145790
    Abstract: A semiconductor light emitting device according to an embodiment includes a stacked body. The stacked body includes a first semiconductor layer of a first conductivity type, a light emitting layer is provided on the first semiconductor layer, and a second semiconductor layer of a second conductivity type provided on the light emitting layer. The stacked body includes a first protrusion on an upper surface of the stacked body. The first protrusion protrudes in a first direction from the first semiconductor layer to the light emitting layer. Length of the first protrusion in a second direction perpendicular to the first direction decreases toward the first direction. The first protrusion includes a first portion and a second portion. The first portion has a first side surface inclined with respect to the first direction. The second portion is provided below the first portion and having a second side surface inclined with respect to the first direction.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 12, 2021
    Assignee: ALPAD CORPORATION
    Inventors: Go Oike, Hiroshi Katsuno, Koji Kaga, Masakazu Sawano, Yuxiong Ren, Kazuyuki Miyabe
  • Patent number: 11145783
    Abstract: An optoelectronic semiconductor component is specified which comprises a semiconductor layer sequence having a first and a second semiconductor layer of a first conductivity type, an active layer designed for generating electromagnetic radiation, a first electrical terminal layer and a second electrical terminal layer laterally spaced therefrom which electrically contacts the second semiconductor layer, and a first contact zone of a second conductivity type which adjoins the first electrical terminal layer and is electrically conductively connected to the first electrical terminal layer. And at least one functional region formed between the first and second terminal layers, in which a second contact zone of a second conductivity type and at least one shielding zone of a second conductivity type is formed. Furthermore, a method for producing the optoelectronic semiconductor component is specified.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: October 12, 2021
    Assignee: OSRAM OLED GMBH
    Inventor: Petrus Sundgren
  • Patent number: 11139418
    Abstract: A light emitting device includes a base including a support having a support surface. A light emitting element includes a semiconductor layer and a sapphire substrate provided on the semiconductor layer opposite to the support surface. A light-transmissive covering member is provided on the sapphire substrate to sandwich the sapphire substrate between the semiconductor layer and the reflecting film. A light emitted from the semiconductor layer is configured to be extracted from the sapphire substrate between the semiconductor layer and the reflecting film. A height of the light-transmissive covering member viewed in a direction in which a width of the light-transmissive covering member appears smallest is 0.5 times or less of the width of the light-transmissive covering member.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: October 5, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Yuichi Yamada, Motokazu Yamada
  • Patent number: 11133305
    Abstract: An approach provides a semiconductor structure for a p-type field effect transistor that includes a nanosheet stack with a top protective layer composed of a plurality of oxygen reservoir layers between a plurality of channel layers, wherein the nanosheet stack is a semiconductor substrate adjacent to one or more isolation structures. The approach includes an interfacial material is around each layer of the plurality of channel layers and on the semiconductor substrate and a layer of gate dielectric material that is over the interfacial material, the top protective layer, and on the one or more isolation structures. The approach includes a layer of a work function metal is over the gate dielectric material and a liner that is over the nanosheet stack and over the work function metal on each of the one or more isolation structures that is covered by a low resistivity metal layer.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Jingyun Zhang, Choonghyun Lee
  • Patent number: 11133446
    Abstract: An optoelectronic component may include an optoelectronic semiconductor chip having an upper side and a lower side. An emitting region may be formed on the upper side. The emitting region may be configured to emit electromagnetic radiation. A subsurface, forming the emitting region, of the upper side may be smaller than a total surface of the upper side. A collimating optical element may be arranged over the emitting region.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 28, 2021
    Assignee: OSRAM OLED
    Inventors: Peter Brick, Stefan Groetsch, Simon Schwalenberg, Michael Wittmann
  • Patent number: 11121300
    Abstract: A method of producing optoelectronic semiconductor devices includes in the stated order: A) providing a semiconductor layer sequence on a transparent wafer, the semiconductor layer sequence including an active layer; B) applying electrical contact pads on a mounting face of the semiconductor layer sequence; C) coating the semiconductor layer sequence at the mounting face and/or on the electrical contact pads with a protective layer; D) dicing the semiconductor layer sequence and the wafer to form semiconductor chips with side faces; E) forming a casting body all around the semiconductor chips directly on the side faces, the protective layer having anti-wetting properties towards a material of the casting body; and F) dicing the casting body to the optoelectronic semiconductor devices, wherein the protective layer remains on the mounting face and/or on the electrical contact pads in the finished optoelectronic semiconductor devices.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 14, 2021
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Chui Wai Chong, Teng Hai Chuah, Seong Tak Koay, Adelene Ng
  • Patent number: 11121173
    Abstract: Techniques for preserving the underlying dielectric layer during MRAM device formation are provided. In one aspect, a method of forming an MRAM device includes: depositing a first dielectric cap layer onto a substrate over logic and memory areas of the substrate; depositing a sacrificial metal layer onto the first dielectric cap layer; patterning the sacrificial metal layer, wherein the patterned sacrificial metal layer is present over the first dielectric cap layer in at least the logic area; depositing a second dielectric cap layer onto the first dielectric cap layer; forming an MRAM stack on the second dielectric cap layer; patterning the MRAM stack using ion beam etching into at least one memory cell, wherein the patterned sacrificial metal layer protects the first dielectric cap layer in the logic area; and removing the patterned sacrificial metal layer. An MRAM device is also provided.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Michael Rizzolo
  • Patent number: 11114455
    Abstract: A method of manufacturing a semiconductor device includes forming holes passing through a stacked structure, surrounding channel structures, and replacing some of the materials of the stacked structure through the holes.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: September 7, 2021
    Assignee: SK hynix inc.
    Inventor: Nam Jae Lee
  • Patent number: 11114537
    Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: September 7, 2021
    Assignee: IMEC VZW
    Inventors: Steve Stoffels, Niels Posthuma, Brice De Jaeger
  • Patent number: 11101403
    Abstract: A surface light source includes a light emitting unit and an optical plate. The optical plate has a light input surface and a light output surface. A side of the optical plate where the light input surface is located have grooves arranged thereon and spaced from one another. A quantum layer is arranged in each of the grooves and includes a colloid and multiple quantum dot nanostructures dispersed in the colloid. Each the quantum dot nanostructure includes an inner core, a ligand layer, a hydrophobic layer, an encapsulation layer and a barrier layer. The light emitting unit includes light sources respectively arranged in the grooves, and a light emitting surface of each the light source is close to the quantum layer so that at least a part of the light rays emitted from the light source is struck onto the quantum layer.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: August 24, 2021
    Assignee: SHENZHEN XIANGYOU TECHNOLOGY CO., LTD
    Inventors: Yuping Wu, Yue Liu
  • Patent number: 11094892
    Abstract: A display device in which damage and carbonization of a display substrate is substantially minimized and a method of manufacturing the display device are provided. A display device includes: a substrate including a first area having a first thickness and a second area having a second thickness which is different from the first thickness; a display layer at the first area of the substrate; and a functional member on the display layer at the first area. The first area and the second area are arranged along a first direction, the substrate includes a protruding portion at the second area, and the protruding portion includes a side portion having an inclination of about 5 degrees or more with respect to the first direction toward a second direction which intersects the first direction.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 17, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Geunwoo Yug
  • Patent number: 11094843
    Abstract: An electrical device that includes a material stack present on a supporting substrate. An LED is present in a first end of the material stack having a first set of bandgap materials. A photovoltaic device is present in a second end of the material stack having a second set of bandgap materials. The first end of the material stack being a light receiving end, wherein a widest bandgap material for the first set of bandgap material is greater than a highest bandgap material for the second set of bandgap materials. A zinc oxide interface layer is present between the LED and the photovoltaic device. The zinc oxide layers or can also form a LED.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendr√° K. Sadana, Ghavam G. Shahidi
  • Patent number: 11088300
    Abstract: An optoelectronic device including: a support; blocks of a semiconductor material, resting on the support and each including a first surface on the side opposite to the support and lateral walls; a nucleation layer on each first surface; a first insulating layer covering each nucleation layer and including an opening exposing a portion of the nucleation layer; a semiconductor element resting on each first insulating layer and in contact with the nucleation layer covered with the first insulating layer in the opening; a shell covering each semiconductor element and including an active layer capable of emitting or absorbing an electromagnetic radiation; and a first conductive layer, reflecting the radiation, extending between the semiconductor elements and extending over at least a portion of the lateral walls of the blocks.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: August 10, 2021
    Assignee: Aledia
    Inventors: Philippe Gibert, Philippe Gilet, Ewen Henaff, Thomas Lacave
  • Patent number: 11081543
    Abstract: Method and apparatus for a capacitive structure. The capacitive structure includes a material stack having a deep trench formed therein. The material stack includes alternating vertical and semi-ovoid sidewall surfaces. The material stack further includes alternating metallization layers and dielectric layers. At least one of the semi-spheroidal sidewall surfaces is formed in a sidewall of at least one of the dielectric layers in the deep trench. At least one of the vertical sidewall surfaces is a sidewall surface of at least one metallization layer in the deep trench.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Praneet Adusumilli, Shanti Pancharatnam, Oscar Van Der Straten
  • Patent number: 11081490
    Abstract: Some embodiments include an integrated assembly having active-region-pillars. Each of the active-region-pillars has contact regions. The contact regions include a pair of storage-element-contact-regions, and include a digit-line-contact-region between the storage-element-contact-regions. The active-region-pillars include silicon. Wordlines are along the active-region-pillars and extend along a first direction. Cobalt silicide is directly against the silicon of one or more of the contact regions. Metal-containing material is directly against the cobalt silicide. Digit-lines are electrically coupled with the digit-line-contact-regions and extend along a second direction which crosses the first direction. Storage-elements are electrically coupled with the storage-element-contact-regions. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Arzum F. Simsek-Ege
  • Patent number: 11075226
    Abstract: The disclosed display device includes: a substrate; a gate electrode disposed on the substrate, wherein a first projection is defined by projecting the gate electrode on the substrate; and a connecting member disposed on the gate electrode and electrically connecting to the gate electrode, wherein a second projection is defined by projecting the connecting member on the substrate, an overlapping region is defined as a region of the second projection overlapping the first projection, and an area of the first projection is greater than an area of the overlapping region.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: July 27, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Yun-Sheng Chen, Hsia-Ching Chu, Ming-Chien Sun
  • Patent number: 11075296
    Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: July 27, 2021
    Assignee: uPI Semiconductor Corp.
    Inventors: Nobuyuki Shirai, Chun-Hsu Chang, Ming-Hung Chou
  • Patent number: 11069734
    Abstract: Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 20, 2021
    Assignee: INVENSAS CORPORATION
    Inventor: Rajesh Katkar