Patents Examined by Mark W Tornow
  • Patent number: 12733304
    Abstract: A display device includes a first electrode and a second electrode on a base layer; a first insulating layer on the first electrode and the second electrode; a bank on the first insulating layer; a light emitting element in an area surrounded by the bank; and a second insulating layer on the bank. The second insulating layer forms an opening exposing a surface of the bank.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: September 8, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin Taek Kim, Hyun Kim, Jeong Su Park, Jong Chan Lee, Woong Hee Jeong, Jung Eun Hong
  • Patent number: 12733107
    Abstract: Embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. The first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: September 8, 2026
    Assignee: Intel Corporation
    Inventors: Jeremy Ecton, Robert Alan May, Suddhasattwa Nad, Srinivas V. Pietambaram, Brandon C. Marin
  • Patent number: 12727289
    Abstract: A display device includes a bank disposed on a substrate, the bank surrounding at least a portion of each of a first emission area and a second emission area in a plan view; first alignment electrodes, at least a number of the first alignment electrodes being disposed in the first emission area; second alignment electrodes, at least a number of the second alignment electrodes being disposed in the second emission area; and a light emitting element disposed in each of the first emission area and the second emission area. An electrode most adjacent to the second emission area among the first alignment electrodes and an electrode most adjacent to the first emission area among the second alignment electrodes are spaced apart from each other with a dividing line disposed therebetween, and the dividing line overlaps the bank in a plan view.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: September 1, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyung Bae Kim, Ji Hye Lee, Jong Woong Chang
  • Patent number: 12727250
    Abstract: An electronic device including a substrate, a data line, a transparent conductive layer, a first light-shielding layer, and a second light-shielding layer is provided. The data line is disposed on the substrate. The transparent conductive layer is disposed on the data line and has a slit, wherein the slit has a trunk portion, and the trunk portion is extended in a first direction. The first light-shielding layer is disposed on the data line and overlapped with the data line. The second light-shielding layer is disposed on the first light-shielding layer. The first light-shielding layer is extended in a second direction, there is a first included angle between the first direction and the second direction, and the first included angle satisfies a following relationship: 0°??1?20°, wherein ?1 is the first included angle.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: September 1, 2026
    Assignee: Innolux Corporation
    Inventors: Wei-Yen Chiu, Yi-Hsiu Wu, Chia-Hao Tsai, Yung-Hsun Wu
  • Patent number: 12727507
    Abstract: The present application provides a substrate encapsulating method, a display panel, and a display device. The substrate encapsulating method includes providing a first underlay, and fabricating a switching device on the first underlay to form a switching substrate; providing a second underlay, and fabricating a light-emitting diode on the second underlay to form a light-emitting substrate; applying a frame glue to an edge of the switching substrate or an edge of the light-emitting substrate; and bonding the switching substrate and the light-emitting substrate with the frame glue to seal the light-emitting diode between the switching substrate and the light-emitting substrate.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: September 1, 2026
    Assignee: Huizhou China Star Optoelectronics Display Co., Ltd.
    Inventors: Changming Xiang, Weiji Zhang
  • Patent number: 12721057
    Abstract: A vacuum packaging manufacturing method includes forming, on a silicon wafer, a lower layer including a first metal layer and a second metal layer formed on the first metal layer, forming anchor regions by etching parts of the second metal layer and depositing a dielectric layer on the second metal layer in which the anchor regions are formed, exposing a silicon oxide film by removing a partial region of the dielectric layer and removing silicon oxide inside the second metal layer covered by the dielectric layer through the removed partial region of the dielectric layer, and depositing an upper layer on the second metal layer and forming a third metal structure on the upper layer, wherein, as the upper layer is deposited on the second metal layer, a region from which the silicon oxide inside the second metal layer is removed is in a vacuum or subvacuum state.
    Type: Grant
    Filed: January 5, 2024
    Date of Patent: August 25, 2026
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventor: Woo Young Choi
  • Patent number: 12707769
    Abstract: The invention relates to an LED package for UV light comprising an optoelectronic device which, in particular as a volume emitter, is designed to emit light in the ultraviolet spectrum during operation. The component is arranged on a carrier with two contact pads for electrical contacting. Furthermore, a frame surrounding the component and arranged on the carrier is provided with a gas-impermeable outlet region lying in a main radiation direction, so that a hermetically sealed cavity comprising an inner region of the carrier is formed, the side walls of the frame facing the optoelectronic device being bevelled and opening towards the main radiation direction. An ESD protection element arranged outside the inner area on the carrier is electrically connected to at least one of the two contact pads.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: August 11, 2026
    Assignee: ams-OSRAM International GmbH
    Inventors: Andreas Reith, Joerg Sorg, Nikolaus Gmeinwieser, Dominik Scholz, Manfred Wolf
  • Patent number: 12696787
    Abstract: A semiconductor device according to the present disclosure includes: a lower arm-side MOSFET; a lower arm-side IGBT; an upper arm-side MOSFET; an upper arm-side IGBT; an upper arm-side IC that controls driving of the upper arm-side MOSFET and the upper arm-side IGBT; a MOSFET gate wire connecting a gate electrode of the upper arm-side MOSFET and the upper arm-side control IC; an IGBT gate wire connecting a gate electrode of the upper arm-side IGBT and the upper arm-side control IC; and an IGBT emitter sense wire directly connecting an emitter electrode of the upper arm-side IGBT and the upper arm-side control IC, and a source electrode of the upper arm-side MOSFET is electrically connected to the upper arm-side control IC via the emitter electrode of the upper arm-side IGBT.
    Type: Grant
    Filed: January 4, 2024
    Date of Patent: July 28, 2026
    Assignee: Mitsubishi Electric Corporation
    Inventors: Toma Takao, Kosuke Yamaguchi
  • Patent number: 12696596
    Abstract: The invention relates to various aspects of a ?-LED or a ?-LED array for augmented reality or lighting applications, in particular in the automotive field. The ?-LED is characterized by particularly small dimensions in the range of a few ?m.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: July 28, 2026
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Andreas Biebersdorf, Michael Brandl, Peter Brick, Jean-Jacques Drolet, Hubert Halbritter, Laura Kreiner, Erwin Lang, Andreas Leber, Marc Philippens, Thomas Schwarz, Julia Stolz, Xue Wang, Karsten Diekmann, Karl Engl, Siegfried Herrmann, Stefan Illek, Ines Pietzonka, Andreas Rausch, Simon Schwalenberg, Petrus Sundgren, Georg Bogner, Christoph Klemp, Christine Rafael, Felix Feix, Eva-Maria Rummel, Nicole Heitzer, Marie Assmann, Christian Berger, Ana Kanevce
  • Patent number: 12684820
    Abstract: A semiconductor structure and its fabrication method. First sacrificial layers are formed on a base substrate. Channel structures are formed on the first sacrificial layers. Each channel structure includes stacked channel stack layer(s). Each channel stack layer includes a second sacrificial layer and a channel layer. Dummy gate structures crossing the channel structures are also formed on the base substrate. Etching resistance of the first sacrificial layers is smaller than etching resistance of the second sacrificial layers. The channel structures and the first sacrificial layers on two sides of each dummy gate structure are removed to form first grooves. The first sacrificial layers at the bottoms of the channel structures are removed to form second grooves connected to the first grooves. Isolation layers are formed in the second grooves; and source-drain doping layers are formed in the first grooves.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: July 14, 2026
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Bo Su, Hanzhu Wu, Abraham Yoo, Haiyang Zhang
  • Patent number: 12684916
    Abstract: A display device includes a display panel including: a transparent substrate; an inorganic light emitting element provided on the transparent substrate and configured to emit a light toward the transparent substrate; a first insulating layer provided on the inorganic light emitting element; and a thin film transistor provided on the first insulating layer; and a driver integrated circuit (IC) configured to drive the display panel, wherein at least a portion of the thin film transistor overlaps at least a portion of the inorganic light emitting element.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: July 14, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donggun Oh, Jinho Kim
  • Patent number: 12684849
    Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, and forming a gate structure to wrap around each of the nanostructures.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: July 14, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Wei-Yang Lee, Ming-Chang Wen, Chien-Tai Chan, Chih Chieh Yeh, Da-Wen Lin
  • Patent number: 12672401
    Abstract: A red LED includes a semiconductor LED layer having an active InGaN layer with intrinsic emission spectrum having LDom in a range of from 580 nm to 620 nm. A filter is positioned over the semiconductor LED layer to filter shorter wavelengths of the intrinsic emission spectrum and shift LDom by between 5 nm to 20 nm to a longer wavelength.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: June 30, 2026
    Assignee: LUMILEDS SINGAPORE PTE. LTD.
    Inventors: Robert Armitage, Isaac Wildeson
  • Patent number: 12672403
    Abstract: Provided is a wavelength converter including a phosphor ceramic containing a first phosphor that emits fluorescence due to a parity-forbidden transition, and a phosphor part containing a second phosphor that emits fluorescence due to a parity-allowed transition. A main surface of the phosphor ceramic has a concave and convex structure including a plurality of convex parts and a plurality of concave parts. The phosphor part is arranged inside the plurality of concave parts in the phosphor ceramic. Also provided is a light emitting device including the wavelength converter, and a solid-state light source that emits light with which the wavelength converter is irradiated and which has a light emission peak within a wavelength range of 400 nm or more and less than 500 nm.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: June 30, 2026
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Mitsuru Nitta, Ryosuke Shigitani, Emi Miyazaki, Toru Hirano
  • Patent number: 12666761
    Abstract: A light-emitting device includes a first semiconductor layer having a first conductive type, an active layer provided on the first semiconductor layer, a second semiconductor layer provided on the active layer and having a second conductive type that is electrically opposite to the first conductive type, an insulating film at least partially surrounding the first semiconductor layer, the active layer, and the second semiconductor layer, and a first plurality of photo-conversion particles provided inside the first semiconductor layer.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: June 23, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sunil Kim, Junhee Choi, Nakhyun Kim, Junghun Park
  • Patent number: 12666775
    Abstract: A chip of a LED, comprising: a current blocking layer including a first current blocking layer grown along an epitaxial layer and a plurality of second current blocking layers disposed at one end of the first current blocking layer at intervals, the first current blocking layer gradually widens along a direction away from the second current blocking layers; a transparent conductive layer including a first transparent conductive layer and a second transparent conductive layer grown on the epitaxial layer, the first transparent conductive layer is grown on the current blocking layer and at least partially overlapped with the second current blocking layers; a metal finger electrode having a width gradually narrowed from the first end to the second end thereof and smaller than the width of the first current blocking layer, and the second current blocking layers are distributed around the first end of the metal finger electrode.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: June 23, 2026
    Assignee: FOCUS LIGHTINGS TECH (SUQIAN) CO., LTD.
    Inventors: Zhiqiang Chu, Hao Chen, Shikang Qu, Zhiqiang Zhang, Chuang Ma, Jie Gao, Zhen Zhang, Qian Zhao, Hebing Wu, Yufei Cao
  • Patent number: 12666769
    Abstract: An LED pump light with multiple phosphors is described. LEDs emitting radiation at violet and/or ultraviolet wavelengths are used to pump phosphor materials that emit other colors. The LEDs operating in different wavelength ranges are arranged to reduce light re-absorption and improve light output efficiency.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: June 23, 2026
    Assignee: KORRUS, INC.
    Inventors: Aurelien J.F. David, Arpan Chakraborty, Michael Ragan Krames, Troy Trottier
  • Patent number: 12666768
    Abstract: An LED lighting base includes an insulation housing and multiple conductive terminals fixed in the insulation housing by means of injection molding. The insulation housing is formed with a recessed compartment for receiving an LED chip assembly and an LED encapsulation resin disposed therein. Each of the conductive terminals includes a solder pad portion extending into the recessed compartment to electrically connect to the LED chip assembly and a pin portion exposed outside the insulation housing. Parts of the pin portions are grouped pairwise to form first pin pairs. One of the first pin pairs is arranged along a first trace and extends in a direction away from the insulation housing, remaining parts of the pin portions are arranged along a second trace. The first trace and the second trace intersect each other.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: June 23, 2026
    Assignee: GUANGDONG OPSCO TECHNOLOGY CO., LTD
    Inventors: Mingjian Liu, Gengsheng Zhu, Zhenlei Wu, Kai Zhou
  • Patent number: 12660433
    Abstract: A display panel is provided, including a metal layer and an elastic conductive layer disposed on a surface of the metal layer. A tensile strength of the elastic conductive layer is greater than a tensile strength of the metal layer. The elastic conductive layer can protect and buffer the metal layer during rolling or bending of the display panel, to effectively avoid the breakage of the metal layer caused by stress concentration.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: June 16, 2026
    Assignees: HUIZHOU CHINA STAR OPTOELECTRONICS DISPLAY CO., LTD., SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Hong Yang
  • Patent number: 12660221
    Abstract: Device structures including a silicon-controlled rectifier and methods of forming a device structure including a silicon-controlled rectifier. The device structure comprises a first well and a second well in a semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite from the first conductivity type. The second well adjoins the first well along an interface. A third doped region includes a first portion in the first well and a second portion in the second well, and a gate structure that overlaps with a portion of the second well.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: June 16, 2026
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Prantik Mahajan, Ajay, Souvick Mitra, Robert J. Gauthier