Patents Examined by Mark W Tornow
  • Patent number: 11728341
    Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11721702
    Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: August 8, 2023
    Assignee: United Microelectronics Corp.
    Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Chung-Liang Chu, Zen-Jay Tsai, Yu-Hsiang Lin
  • Patent number: 11716896
    Abstract: There is provided a photoelectric conversion film including a quinacridone derivative represented by the following General formula and a subphthalocyanine derivative represented by the following General formula.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: August 1, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshiaki Obana, Yuki Negishi, Yuta Hasegawa, Ichiro Takemura, Osamu Enoki, Hideaki Mogi, Nobuyuki Matsuzawa
  • Patent number: 11711896
    Abstract: An electronic device is provided, the electronic device includes a driving substrate, the driving substrate includes a plurality of circular grooves and a plurality of rectangular grooves, a plurality of disc-shaped light-emitting units, at least one disc-shaped light-emitting unit is disposed in at least one circular groove, and the at least one disc-shaped light-emitting unit includes an alignment element positioned on a top surface of the at least one disc-shaped light-emitting unit, a diameter of the at least one disc-shaped light-emitting unit is defined as R, a diameter of the alignment element is defined as r, a width of at least one rectangular groove among the rectangular grooves is defined as w, and a height of the at least one rectangular groove is defined as H, and the at least one disc-shaped light-emitting unit and the at least one rectangular groove satisfy the condition of (R+r)/2>(w2+H2)1/2.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: July 25, 2023
    Assignee: InnoLux Corporation
    Inventor: Chun-Hsien Lin
  • Patent number: 11705477
    Abstract: A display device and a method of fabricating the same are provided. The display device includes a substrate, a first electrode on the substrate, a second electrode on the substrate and spaced apart from the first electrode, a plurality of light emitting elements, at least a portion of each of which is between the first electrode and the second electrode, and contact electrodes on the first electrode, the second electrode and the light emitting elements, the contact electrodes including a conductive polymer, wherein the contact electrodes include a first contact electrode which contacts an end portion of a first portion of the light emitting elements and the first electrode and a second contact electrode which contacts an end portion of a second portion of the light emitting elements, and the second electrode and is spaced apart from the first contact electrode.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: July 18, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Si Kwang Kim, Min Suk Ko, Kab Jong Seo, Yong Hoon Yang
  • Patent number: 11705400
    Abstract: A semiconductor package includes: a first substrate; a semiconductor chip mounted on the first substrate such that a circuit formation surface is oriented toward the first substrate; a second substrate arranged above the first substrate, the semiconductor chip being sandwiched between the first substrate and the second substrate; and a resin that seals the semiconductor chip and that is filled between the first substrate and the second substrate, wherein the second substrate includes a solder resist layer having a first surface facing a back surface that is an opposite surface of the circuit formation surface of the semiconductor chip, and wherein on an area of the first surface of the solder resist layer facing the back surface of the semiconductor chip, at least one protruding portion that protrudes towards the back surface of the semiconductor chip is provided.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: July 18, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Seiji Sato
  • Patent number: 11705514
    Abstract: A MOS transistor structure is provided. The MOS transistor structure includes a semiconductor substrate having an active area including a first edge and a second edge opposite thereto. A gate layer is disposed on the active area of the semiconductor substrate and has a first edge extending across the first and second edges of the active area. A source region having a first conductivity type is in the active area at a side of the first edge of the gate layer and between the first and second edges of the active area. First and second heavily doped regions of a second conductivity type are in the active area adjacent to the first and second edges thereof, respectively, and spaced apart from each other by the source region.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 18, 2023
    Assignee: MediaTek Inc.
    Inventors: Cheng Hua Lin, Yan-Liang Ji
  • Patent number: 11705542
    Abstract: Solid-state lighting devices including light-emitting diodes (LEDs), and more particularly binder materials for light-emitting devices are disclosed. A lumiphoric material for a light-emitting device may include lumiphoric particles embedded within a binder material. The lumiphoric material may be formed according to sol-gel chemistry techniques where a solution of binder precursors and lumiphoric particles is applied to a surface, dried to reduce liquid phase, and fired to form a hardened and dense lumiphoric material. The binder precursors may include metal oxide precursors that result in a metal oxide binder. In this manner, the lumiphoric material may have high thermal conductivity while also being adaptable for liquid-phase processing. In further embodiments, binder materials with or without lumiphoric particles may be utilized in place of conventional encapsulation materials for light-emitting devices.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: July 18, 2023
    Assignee: CreeLED, Inc.
    Inventors: Walter Weare, Derek Miller, Brian T. Collins, Colin Blakely
  • Patent number: 11699775
    Abstract: A semiconductor light emitting diode (LED) and a method of manufacturing the same are provided. The LED includes a first semiconductor layer; a plurality of active elements spaced apart on the first semiconductor layer and each having a width less than a width of the first semiconductor layer; and a second semiconductor layer disposed on the plurality of active elements.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: July 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO.. LTD.
    Inventors: Junhee Choi, Nakhyun Kim, Jinjoo Park, Joohun Han
  • Patent number: 11695031
    Abstract: A light-emitting device is provided. The light emitting device includes a support substrate having a light-emitting cell region, a pad region and an edge region, the edge region surrounding the light-emitting cell region and the pad region; a plurality of unit light-emitting devices arranged in a matrix in the light-emitting cell region and spaced apart from each other; a plurality of pads formed in the pad region; partition walls arranged on the plurality of unit light-emitting devices, the partition walls defining a plurality of cell spaces respectively corresponding to the plurality of unit light-emitting devices; and a plurality of fluorescent layers arranged on the plurality of unit light-emitting devices in the plurality of cell spaces. The light-emitting device has a cuboid shape, in which a first length in a first direction is greater than a second length in a second direction.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: July 4, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungwook Lee, Jaeyoon Kim, Sangbum Lee, Sungwook Lee, Sumin Hwangbo
  • Patent number: 11688840
    Abstract: A light emitting device including a first light emitting stack, a second light emitting stack disposed under the first light emitting stack, a third light emitting stack disposed under the second light emitting stack, first, second, third, and fourth connection electrodes disposed over the first light emitting stack, and electrically connected to the first, second, and third light emitting stacks, and bonding metal layers disposed on upper surfaces of the first, second, third, and fourth connection electrodes, in which each of the first, second, third, and fourth connection electrodes includes a groove on an upper surface thereof, and the bonding metal layers cover the grooves of the first, second, third, and fourth connection electrodes, respectively.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 27, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Sung Hyun Lee, Chang Yeon Kim
  • Patent number: 11688699
    Abstract: Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling region. A support material is adjacent the first and second sets of the memory cells, and an intervening material is adjacent the support material. The support material has a different composition than the intervening material. A conductive interconnect extends through the intervening material. An upper surface of the assembly is polished to reduce an overall height of the assembly. The support material provides support during the polishing to protect the memory cells from being eroded during the polishing. The conductive interconnect of the second tier is coupled with the CMOS circuitry of the first tier. Some embodiments include multitier arrangements.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Mihir Bohra, Tarun Mudgal
  • Patent number: 11676873
    Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Dinesh Padmanabhan Ramalekshmi Thanu, Hemanth K. Dhavaleswarapu, Venkata Suresh Guthikonda, John J. Beatty, Yonghao An, Marco Aurelio Cartas Ayala, Luke J. Garner, Peng Li
  • Patent number: 11661549
    Abstract: A phosphor having a favorable emission peak wavelength, narrow full width at half maximum, and/or high emission intensity is provided. Additionally, a light-emitting device, an illumination device, an image display device, and/or an indicator lamp for a vehicle having favorable color rendering, color reproducibility and/or favorable conversion efficiency are provided. The present invention relates to a phosphor including a crystal phase having a composition represented by a specific formula, and when, in a powder X-ray diffraction spectrum of the phosphor, the intensity of a peak that appears in a region where 2?=38-39° is designated as Ix and the intensity of a peak that appears in a region where 2?=37-38° is designated as Iy, the relative intensity Ix/Iy of Ix to Iy is 0.140 or less, and a light-emitting device comprising the phosphor.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 30, 2023
    Assignees: Mitsubishi Chemical Corporation, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Tomoyuki Kurushima, Yuhei Inata, Naoto Hirosaki
  • Patent number: 11664353
    Abstract: A light-emitting device according to an embodiment is provided with: a light-emitting panel including a first board that is light transmissive and flexible, a plurality of conductor patterns formed on a surface of the first board, a plurality of light-emitting elements connected to one of the conductor patterns, and a second board that is light transmissive and flexible and that holds the light-emitting elements relative to the first board; and a flexible wiring board including a circuit pattern that is electrically connected via an anisotropic conductive layer to an exposed part of the conductor patterns formed on the first board, the exposed part being exposed by the end of the second board.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: May 30, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Kairi Makita, Fumio Ueno
  • Patent number: 11658132
    Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Lifang Xu, Jian Li
  • Patent number: 11655416
    Abstract: A phosphor having a favorable emission peak wavelength, narrow full width at half maximum, and/or high emission intensity is provided. Additionally, a light-emitting device, an illumination device, an image display device, and/or an indicator lamp for a vehicle having favorable color rendering, color reproducibility and/or favorable conversion efficiency are provided. The present invention relates to a phosphor including a crystal phase having a composition represented by a specific formula, and having a minimum reflectance of 20% or more in a specific wavelength region, in which the specific wavelength region is from the emission peak wavelength of the phosphor to 800 nm, and a light-emitting device comprising the phosphor.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 23, 2023
    Assignees: Mitsubishi Chemical Corporation, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Tomoyuki Kurushima, Yuhei Inata, Naoto Hirosaki
  • Patent number: 11658259
    Abstract: A light emitting device is provided. The light emitting device includes a first semiconductor layer; a second semiconductor layer provided on a bottom surface of the first semiconductor layer; an active layer interposed between the first semiconductor layer and the second semiconductor layer; a dielectric layer provided on a bottom surface of the second semiconductor layer; a plurality of first n-contacts provided on a first etched surface of the first semiconductor layer; and a plurality of first p-contacts and a plurality of second p-contacts provided on the bottom surface of the second semiconductor layer. One first n-contact is disposed along a first edge region of the first semiconductor layer, one first p-contact is closer to the one first n-contact than one second p-contact, and an area of the one first p-contact is greater than an area of each of the second p-contacts.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeonghwan Jang, Jae-Yoon Kim, Sungwon Ko, Junghee Kwak, Sangseok Lee, Suyeol Lee, Seungwan Chae, Pun Jae Choi
  • Patent number: 11658276
    Abstract: An electronic device including a light emitting element, a wavelength conversion layer, a conductive wire and a wavelength selection layer is provided by the present disclosure. The light emitting element is configured to emit a light. The wavelength conversion layer is configured to convert the light. The conductive wire is electrically connected to the light emitting element. The wavelength selection layer is disposed between the conductive wire and the wavelength conversion layer, wherein the conductive wire is cured by an energy beam, and the wavelength selection layer is configured to block the energy beam.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: May 23, 2023
    Assignee: InnoLux Corporation
    Inventors: Wan-Ling Huang, Shu-Ming Kuo, Tsau-Hua Hsieh, Tzu-Min Yan
  • Patent number: 11658205
    Abstract: An electroluminescent display device includes a substrate on which a display area and a non-display area are defined, a plurality of sub-pixels disposed in the display area on the substrate and arranged along a first direction and a second direction, a light-emitting diode disposed at each of the plurality of sub-pixels and including a first electrode, a light-emitting layer and a second electrode, a first bank disposed between adjacent sub-pixels arranged along the second direction and overlapping edges of the first electrode, and a second bank disposed between adjacent sub-pixels arranged along the first direction and having an opening corresponding to a row of the sub-pixels arranged along the second direction, wherein the opening includes a first portion corresponding to the display area and a second portion corresponding to the non-display area, and a width of the second portion is narrower than a width of the first portion.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: May 23, 2023
    Assignee: LG Display Co., Ltd.
    Inventor: Jeong-Mook Choi