Abstract: In some embodiments, a semiconductor structure comprises a semiconductor layer, a metal layer, and a contact layer adjacent to the metal layer, and between the semiconductor layer and the metal layer. The contact layer can comprise one or more piezoelectric materials comprising spontaneous piezoelectric polarization that depends on material composition and/or strain, and a region comprising a gradient in materials composition and/or strain adjacent to the metal layer. In some embodiments, a light emitting diode (LED) device comprises an n-doped short period superlattice (SPSL) layer, an intrinsically doped AlN/GaN SPSL layer adjacent to the n-doped SPSL layer, a metal layer, and an ohmic-chirp layer between the metal layer and the intrinsically doped AlN/GaN SPSL layer.

Abstract: An optoelectronic device including: a three-dimensional semiconductor element mostly made of a first chemical element and of a second chemical element; an active area at least partially covering the lateral walls of the three-dimensional semiconductor element and including a stack of at least a first layer mostly made of the first and second chemical elements, and of at least a second layer mostly made of the first and second chemical elements and of a third chemical element; a third layer covering the active area, the third layer being mostly made of the first, second, and third chemical elements and of a fourth chemical element, the mass proportion of the third and fourth chemical elements of the third layer increasing or decreasing as the distance to the substrate increases; and a fourth layer, mostly made of the first and second chemical elements, covering the third layer.

Abstract: An optoelectronic component is disclosed. In an embodiment an optoelectronic component includes a semiconductor chip configured to emit radiation and a conversion element including quantum dots, the conversion element configured to convert a wavelength of the radiation, wherein each quantum dot includes a wavelength-converting core and an inorganic encapsulation, wherein inorganic encapsulations form a matrix material of at least adjacent quantum dots, and wherein the adjacent quantum dots have a distance of at least 10 nm.

Abstract: An image pickup device having a pixel region in which pixels are arranged, and in which a multilayer wiring structure is disposed. Each pixel includes a photoelectric conversion unit, a charge accumulation unit, a floating diffusion, a light shielding portion covering the charge accumulation unit and opening above the photoelectric conversion unit, and a waveguide which overlaps at least partially a portion at which the light shielding portion opens in a plan view. The device includes an insulating film disposed below the optical waveguide. The insulating film has a refractive index higher than that of an interlayer insulating film. The insulating film is disposed closer to the photoelectric conversion unit than to the lowermost wiring layer among wiring layers of the multilayer wiring structure. The insulating film extends to a portion above the light shielding portion. The insulating film is wider than a lower portion of the optical waveguide.

Abstract: A quantum dot including a core that includes a first semiconductor nanocrystal including zinc and selenium, and optionally sulfur and/or tellurium, and a shell that includes a second semiconductor nanocrystal including zinc, and at least one of sulfur or selenium is disclosed. The quantum dot has an average particle diameter of greater than or equal to about 13 nm, an emission peak wavelength in a range of about 440 nm to about 470 nm, and a full width at half maximum (FWHM) of an emission wavelength of less than about 25 nm. A method for preparing the quantum dot, a quantum dot-polymer composite including the quantum dot, and an electronic device including the quantum dot is also disclosed.

Abstract: A light emitting diode includes an n-type nitride semiconductor layer, a V-pit generation layer located over the n-type nitride semiconductor layer and having a V-pit, an active layer located on the V-pit generation layer, and a p-type nitride semiconductor layer located on the active layer. The active layer includes a well layer, which includes a first well layer portion formed along a flat surface of the V-pit generation layer and a second well layer portion formed in the V-pit of the V-pit generation layer. The light emitting diode emits light having at least two peak wavelengths at a single chip level.

Abstract: A LED light display having a plurality of LED bulb arrays and a louver panel defining a plurality of hole arrays. Each hole array can define openings that are sized and spaced to receive at least the distal end portions of the bulbs forming a single LED bulb array. The louver panel further has a plurality of shaped protrusions in the form of louvers that are configured to extend outwardly and forwardly from a front surface of the louver panel and are arranged in a plurality of columns and in a plurality of rows in regularly repeating patterns related to the pattern of the placement of a plurality of the plurality of hole arrays in the louver panel and are further configured to block at least a portion of the emission of light from the LED bulbs in both a horizontal and vertical direction.

Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

Abstract: A light emitting apparatus includes an electrode and a laminated structure. The laminated structure includes an n-type first semiconductor layer, a light emitting layer, a p-type second semiconductor layer, a tunnel junction layer, and an n-type third semiconductor layer. The electrode is electrically connected to the first semiconductor layer. The first semiconductor layer, the light emitting layer, the second semiconductor layer, the tunnel junction layer, and the third semiconductor layer are arranged in a presented order. The light emitting layer and the first semiconductor layer form a columnar section.

Abstract: A method of manufacturing a semiconductor device includes forming holes passing through a stacked structure, surrounding channel structures, and replacing some of the materials of the stacked structure through the holes.

Abstract: According to one embodiment, a display device includes first semiconductor layers crossing a first scanning line in a non-display area, the first semiconductor layers being a in number, second semiconductor layers crossing a second scanning line in the non-display area, the second semiconductor layers being b in number, and an insulating film disposed between the first and second semiconductor layers and the first and second scanning lines, wherein a and b are integers greater than or equal to 2, and a is different from b, and the first and second semiconductor layers are both entirely covered with the insulating film.

Abstract: A LED package comprises an LED chip, a reflective structure which encloses the LED chip, a wavelength conversion structure placed on the LED chip, and an absorbing structure which encloses or is placed on the reflective structure.

Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.

Abstract: A guard ring structure includes a plurality of first groups of concentric guard rings encompassing an active region of an integrated circuit, the concentric guard rings of the first groups having a guard ring pitch of less than 80 nm. The concentric guard rings of the first groups have a single, closed path that is distinct from an adjacent guard ring and defines a rectangular geometry with rounded corners. Second groups of guard rings are interspersed with and concentrically arranged with the first groups, where each corner region of the second groups include at least one guard ring defect. A method of fabricating a guard ring structure for an integrated circuit is also disclosed.

Abstract: An optoelectronic semiconductor chip may include an active region configured to emit electromagnetic radiation during operation of said optoelectronic semiconductor chip. The optoelectronic semiconductor chip comprises conversion elements arranged to convert the wavelength of the electromagnetic radiation emitted by the active region during operation, and at least one barrier at least partially impermeable to the electromagnetic radiation emitted by the active region. The barrier is disposed in a lateral direction between the conversion elements, the lateral direction being parallel to the main extension plane of the semiconductor body, and the barrier extending transversely to the lateral direction. The active region has at least two emission regions which can be driven separately from each other, and each of the conversion elements is disposed in a radiation direction of the electromagnetic radiation emitted from one of the emission regions.

Abstract: A wavelength converting structure is disclosed, the wavelength converting structure including an SWIR phosphor material having emission wavelengths in the range of 1000 to 1700 nm, the SWIR phosphor material including at least one of a perovskite type phosphor doped with Ni2+, a perovskite type phosphor doped with Ni2+ and Cr3+, and a garnet type phosphor doped with Ni2+ and Cr3+.

Abstract: An epitaxial light emitting structure includes n-type and p-type semiconductor layers, and a light emitting component disposed therebetween. The light emitting component includes a multiple quantum well structure which contains a plurality of first periodic layered elements, each of which includes first, second and third layers alternately stacked on one another. For each of the first periodic layered elements, the first, second and third layers respectively have a first energy bandgap (Eg1), a second energy bandgap (Eg2), and a third energy bandgap (Eg3) that satisfy a relationship of Eg1<Eg2<Eg3. Also disclosed herein is a light emitting diode which includes the aforementioned epitaxial light emitting structure.

Abstract: An embodiment discloses a semiconductor device package comprising: a body including a cavity; a semiconductor device disposed in the cavity; a light transmitting member disposed in the cavity; and an adhesive layer for fixing the light transmitting member to the body, wherein the semiconductor device generates light in an ultraviolet wavelength band, and the adhesive layer comprises polymer resin and wavelength conversion particles which absorb the light in the ultraviolet wavelength band and generate light in a visible wavelength band.

Abstract: Substrate, display panel and assembly detection method thereof are provided. The substrate includes a supporting base and a plurality of sub-pixel areas arranged in an array. A main conductive pad unit and a spare conductive pad unit are formed on the supporting base in each sub-pixel area. An anti-reflection layer is disposed on a side of the supporting base adjacent to the main conductive pad unit and the spare conductive pad unit. An orthographic projection of the anti-reflection layer on the supporting base at least covers an orthographic projection of the spare conductive pad unit on the supporting base.

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.