Abstract: Disclosed is a method for automating testing tasks which would otherwise have to be done manually using actual hardware by providing the capability to dynamically create many types of storage devices with different storage media, thus eliminating the need to have test machines with the actual hardware. In one embodiment a virtual storage device driver can be implemented that can be used to simulate various storage devices such as CD-ROM, CD-R, CD-RW, removable disk drives and fixed disk drives. Manual testing tasks such as testing autoplay functionality when a CD is inserted, testing CD burning, and testing CD audio playback can then be automated.
Abstract: A system for controlling contention between conflicting transactions in a transactional memory system. During operation, the system receives a request to access a cache line and then determines if the cache line is already in use by an existing transaction in a cache state that is incompatible with the request. If so, the system determines if the request is from a processor which is in a polite mode. If this is true, the system denies the request to access the cache line and continues executing the existing transaction.
Type:
Grant
Filed:
April 18, 2005
Date of Patent:
February 24, 2009
Assignee:
Sun Microsystems, Inc.
Inventors:
Daniel S. Nussbaum, Victor M. Luchangco, Mark S. Moir, Ori Shalev, Nir N. Shavit
Abstract: An apparatus, system, and method are disclosed for reliably updating a data group in a data replication environment. The apparatus, system, and method reliably update the data group by receiving an updated data group sent from a first storage medium to a second storage medium, comparing the updated data group with a previous data group previously existing on the second storage medium and writing the updated data group to the second storage medium. The read-before-write and differencing method disclosed maintain reliability by storing multiple copies of changes made to the second storage medium during and after the write process.
Type:
Grant
Filed:
March 30, 2005
Date of Patent:
January 27, 2009
Assignee:
International Business Machines Corporation
Inventors:
Henry Esmond Butterworth, Kenneth Fairclough Day, III, Philip Matthew Doatmas, John Jay Wolfgang, Vitaly Zautner, Aviad Zlotnick
Abstract: An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies the memory device voltage in response to the change of the memory device stress. In one embodiment, a processor pause module pauses the operation of a processor module while the timing modification module modifies the memory device timing and the voltage modification module modifies the memory device voltage.
Type:
Grant
Filed:
June 9, 2005
Date of Patent:
October 28, 2008
Assignee:
International Business Machines Corporation
Inventors:
Moises Cases, Daniel N. de Araujo, Nam Huu Pham, Menas Roumbakis
Abstract: One embodiment of the present invention provides a system that avoids locks by transactionally executing critical sections. During operation, the system receives a program which includes one or more critical sections which are protected by locks. Next, the system modifies the program so that the critical sections which are protected by locks are executed transactionally without acquiring locks associated with the critical sections.
Type:
Grant
Filed:
August 1, 2005
Date of Patent:
July 8, 2008
Assignee:
Sun Microsystems, Inc.
Inventors:
Mark S. Moir, Marc Tremblay, Shailender Chaudhry
Abstract: Exemplary embodiments relate to methods, systems, and storage mediums for managing content storage and selection activities. The method includes monitoring consumption of storage space with respect to storage capacity in at least one content device receiving content from a content provider, relocating content contained in the storage space of the content device when a predetermined condition is met, and providing access to relocated content. The relocation is operable for freeing up the storage space of the content device.
Type:
Grant
Filed:
November 9, 2004
Date of Patent:
July 1, 2008
Assignee:
AT&T Delaware Intellectual Property, Inc.
Abstract: One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered.
Type:
Grant
Filed:
April 6, 2006
Date of Patent:
June 17, 2008
Assignee:
Sun Microsystems, Inc.
Inventors:
Marc Tremblay, Quinn A. Jacobson, Shailender Chaudhry, Mark S. Moir, Maurice P. Herlihy
Abstract: A method for controlling data flow to a pair of storage devices includes receiving at least one new entry to store in a first storage device or a second storage device in the pair of storage devices and determining a number of entries made to the first and second storage devices out of the at least one new entry. The method also includes calculating a difference between available space in the first storage device and the second storage device, and calculating a number of credits used by the at least one new entry based on the numbers of entries to the first and second storage devices and on the difference in available space.
Type:
Grant
Filed:
January 10, 2005
Date of Patent:
May 27, 2008
Assignee:
Hewlett-Packard Development Company, L.P.
Abstract: A cross compare solution running in a multiprocessor configuration, using a multi-port RAM with built-in logic. This provides for a fast and simple data cross compare medium. The multi-port RAM unit can be plugged into the motherboard of the main processor unit, requiring no external hardware or wiring. A method and a system for cross compare has a first layer of buffers with a first storage area for storing information from the first processor and a second storage area for storing information from the second processor, and a second layer of buffers with a third and fourth storage areas, where each storage area stores information from the first and second storage areas. The first, second, third, and fourth storage areas have one or more buffers allocated only for its respective storage area.
Type:
Grant
Filed:
December 3, 2004
Date of Patent:
March 25, 2008
Assignee:
Thales
Inventors:
Mario Popescu, Stephen Barr, Alexander Trica
Abstract: A clustered storage array consists of several nodes coupled to one or more storage systems. The nodes provide a LUN-device for access by a client, the LUN-device mapping to a source logical unit corresponding to areas of storage on the one or more storage systems. A target logical unit corresponds to different areas of storage on the one or more storage systems. The source logical unit is migrated in parallel by the several nodes to the target logical unit.
Type:
Grant
Filed:
December 20, 2004
Date of Patent:
March 11, 2008
Assignee:
EMC Corporation
Inventors:
Michael F. Brown, Kiran P. Madnani, David W. DesRoches
Abstract: A method includes stalling a call to a heap allocation function originating from a request by an application for a block of heap buffer, predicting a block of the heap buffer to fulfill the request, and determining if a forward link (F-link) and a backward link (B-link) of the predicted block are addresses within a heap segment associated with the predicted block. If a determination is made that the F-link or the B-link point outside the associated heap segment, e.g., have been overwritten by a heap buffer overflow attack, corrective action is taken to correct the stray F-link or B-link. After the corrective action is taken, the heap allocation function call is released and the block of heap buffer is allocated. In this manner, a heap buffer overflow attack is defeated.
Abstract: In one embodiment, a storage subsystem includes a plurality of storage arrays each including a plurality of storage devices. The storage subsystem also includes a plurality of array controllers each coupled to one or more of the plurality of storage arrays. One or more of the arrays corresponds to a failure group. Each array controller may create a storage volume including storage devices belonging to one or more of plurality of storage arrays. In addition, the storage subsystem includes a redundancy controller that may be configured to implement N+K redundancy. The redundancy controller includes configuration functionality that may determine a number of redundant system data blocks to be stored on different storage devices for a given stripe of data that is dependent upon particular values of N and K and upon physical system configuration information.
Abstract: Concurrent read access and exclusive write access are provided in a shared memory architecture to permit one or more devices in the shared memory architecture to maintain read access to a block of memory such as a cache line while one device has exclusive permission to modify that block of memory. By doing so, a device that has permission to modify may make updates to its copy of the block of memory without invalidating other copies of the block of memory, and potentially enabling other devices to continue to read data from their respective copies of the block of memory without having to retrieve the updated copy of the block of memory.
Type:
Grant
Filed:
December 17, 2004
Date of Patent:
December 11, 2007
Assignee:
International Business Machines Corporation
Inventors:
Ronald Edward Fuhs, Ryan Scott Haraden, Nathaniel Paul Sellin, Scott Michael Willenborg
Abstract: Disclosed is an adaptive maximum request size process to change the maximum request size for a RAID system in order to reflect the highest possible maximum request size permitted by the RAID type and the physical drives included in the RAID system. The maximum request size is a primary limiting characteristic for physical drive and logical drive performance. The logical drive maximum request size is limited by the physical drive maximum request size. Physical drives supporting older revisions of the physical drive standards have a much lower maximum request size than physical drives supporting newer revisions of the physical drive standard. The adaptive maximum request size process permits a RAID system to adjust the maximum request size to reflect the highest possible maximum request size allowed for a given system based on the physical drives of the RAID system and the RAID types of all RAID logical drives.
Abstract: A garbage collector that reclaims memory for a mutator does so space-incrementally, employing remembered sets associated with respective heap regions to keep track of where the mutator has notified it of writing references into the associated regions. The collector reserves some heap regions for objects that it has found to be “popular,” i.e., to which it has observed a large number of references. When the mutator writes such a reference, it refrains from making the kind of notification to which the garbage collector would otherwise respond by updating a remembered set. Although this deprives the garbage collector of the ability to maintain complete remembered sets for popular-object regions, those regions usually have no unreachable objects or very few, so the collector can dispense with collecting them or can collect them less frequently, in a way that does not rely on remembered sets.