Abstract: Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.
Type:
Grant
Filed:
November 19, 2008
Date of Patent:
May 20, 2014
Assignee:
Oracle America, Inc.
Inventors:
Robert E. Cypher, Haakan E. Zeffer, Shailender Chaudhry
Abstract: Various method, system, and computer program product embodiments for performing a backup of a source storage volume to a target storage volume are provided. In one exemplary embodiment, a flashcopy of the source storage volume to the target storage volume is initiated. The content of the source storage volume is stored on the target storage volume in a space efficient manner. The space requirement of the stored content on the target storage volume is monitored. The flashcopy is terminated when the space requirement reaches a predetermined level. The stored content on the target storage volume is copied to a backup storage medium. A new flashcopy of the source storage volume is initiated.
Type:
Grant
Filed:
September 14, 2012
Date of Patent:
May 13, 2014
Assignee:
International Business Machines Corporation
Inventors:
Gordon D. Hutchison, Cameron J. McAllister, Lucy Raw, Bruce J. Smith
Abstract: Devices, systems, methods, and other embodiments associated with selectively accessing memory are described. In one embodiment, a method detects an indication indicative of whether to program fast access pages or slow access pages of a flash memory. In response to the detected indication, data is programmed from a volatile memory: (1) to the fast access pages of the flash memory while skipping the slow access pages, or (2) to the slow access pages while skipping the fast access pages.
Abstract: A storage resource is effectively utilized in migration of a snapshot. First de-duplication efficiency which is de-duplication efficiency of snapshot data, and second de-duplication efficiency which is de-duplication efficiency of snapshot entities created on the basis of the snapshot data are calculated and compared with each other. Based on a result of the comparison as well as a first preservation period set for the snapshot in the migration source and a second preservation period set for the snapshot in the migration destination, one of the following methods is selected: a first method of migrating an snapshot image, a second method of migrating snapshot data to an archive storage system, and a third method of migrating data materialized from a first differential volume, a second differential volume, and a switch snapshot.
Abstract: Methods and systems are herein disclosed for write operation retry using the data stored and retained in an internal buffer within the non-volatile memory device. By using the data stored in the internal buffer, the systems and method of the present invention eliminate the need to include a dedicated retry buffer at the system level. Thereby, reducing the system cost, minimizing space consumption on a board within the system and, in some instance, limiting the latency attributed to a retry that relies on retrying the write based on re-transferring of the data contents to the internal non-volatile memory buffer.
Abstract: Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.
Type:
Grant
Filed:
July 20, 2012
Date of Patent:
April 1, 2014
Assignee:
Microsoft Corporation
Inventors:
Koichi Yamada, Gad Sheaffer, Ali-Reza Adl-Tabatabai, Landy Wang, Martin Taillefer, Arun Kishan, David Callahan, Jan Gray, Vadim Bassin
Abstract: A device for managing multiple instructions to access multiple wide registers may include logic to receive the multiple instructions to access one of the multiple wide registers, associate each received instruction with a corresponding one of multiple buffer memories, and allow simultaneous processing of the multiple instructions associated with each of the multiple buffer memories, where the multiple instructions are processed such that data is transferred between the multiple buffer memories and the multiple wide registers in one operation.
Type:
Grant
Filed:
June 28, 2007
Date of Patent:
March 18, 2014
Assignee:
Juniper Networks, Inc.
Inventors:
Karthikeyan Veerabadran, David J. Ofelt
Abstract: A system and method for communicating, browsing, verifying and routing data in storage operation systems using network attached storage devices is provided. In some embodiments, the system may include a management module and a media management component connected to the management server, which interoperate with network attached storage devices to provide the communicating, browsing, verifying and routing functions.
Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
Type:
Grant
Filed:
June 28, 2007
Date of Patent:
February 4, 2014
Assignee:
EMC Corporation
Inventors:
John O'Shea, Jeffrey Kinne, Michael Sgrosso, Steven T. McClure, Yechiel Yochai
Abstract: An apparatus, system, and method are disclosed for determining prefetch data. A start module communicates a start of a target software process to a storage device. A learning module learns data blocks accessed for the target software process. In one embodiment, a prefetch module prefetches the learned data blocks in response to the start of the target software process. An end module communicates the end of the target software process to the storage device. In one embodiment, the prefetch module terminates prefetching data blocks and the learning module terminates learning the data blocks accessed for the target software process in response to the end module's communication of the end of the target software process.
Type:
Grant
Filed:
February 17, 2006
Date of Patent:
December 10, 2013
Assignee:
International Business Machines Corporation
Inventors:
Kenneth Wayne Boyd, Kenneth Fairclough Day, III, David Allan Pease, John Jay Wolfgang
Abstract: An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.
Type:
Grant
Filed:
September 2, 2008
Date of Patent:
November 26, 2013
Assignee:
Qimonda AG
Inventors:
Michael Kund, Thomas Happ, GillYong Lee, Heinz Hoenigschmid, Rolf Weis, Christoph Ludwig
Abstract: Systems and methods for managing a virtual tape library (VTL) domain capable of being coupled to a host are provided. One system includes a plurality of VTL nodes configured to store multiple scratch erased volumes. Each VTL node comprises a processor configured to perform at least a portion of the below method. One method includes receiving a request from the host to de-mount a volume in one of the plurality of VTL nodes, transferring the volume to a scratch category in response to receiving the request, erasing data in the volume and categorizing the volume as a scratch erased volume, and providing ownership of the scratch erased volume to a VTL node in the plurality of VTL nodes based on pre-determined criteria for the plurality of VTL nodes. Also provided are computer storage mediums including computer code for performing the above method.
Type:
Grant
Filed:
September 30, 2010
Date of Patent:
November 26, 2013
Assignee:
International Business Machines Corporation
Abstract: A computer system having a plurality of host computers and a storage system is provided which allows any one host computer to perform a global copy operation on any arbitrary or all storage areas in the storage system. To this end, storage areas provided by the disk devices are grouped into groups by allocating group numbers to a plurality of specified storage areas. The copy operation can be performed by specifying desired groups. Each of the groups is made up of sub-groups and the sub-groups are defined for each computer to assure a consistency of copy order of the sub-groups.
Abstract: A method is disclosed for reliably updating a data group in a read-before-write data replication environment. The method reliably updates the data group by receiving an updated data group sent from a first storage medium to a second storage medium, comparing the updated data group with a previous data group previously existing on the second storage medium and writing the updated data group to the second storage medium. The read-before-write and differencing method disclosed maintain reliability by storing multiple copies of changes made to the second storage medium during and after the write process.
Type:
Grant
Filed:
October 30, 2008
Date of Patent:
October 29, 2013
Assignee:
International Business Machines Corporation
Inventors:
Henry Esmond Butterworth, Kenneth Fairclough Day, III, Philip Matthew Doatmas, John Jay Wolfgang, Vitaly Zautner, Aviad Zlotnick
Abstract: A flashcopy of a source storage volume to a target storage volume is initiated. The content of the source storage volume is stored on the target storage volume in a space efficient manner. The space requirement of the stored content on the target storage volume is monitored. The flashcopy is terminated when the space requirement reaches a predetermined level. The stored content on the target storage volume is copied to a backup storage medium. A new flashcopy of the source storage volume is initiated.
Type:
Grant
Filed:
May 3, 2012
Date of Patent:
October 15, 2013
Assignee:
International Business Machines Corporation
Inventors:
Gordon D. Hutchison, Cameron J. McAllister, Lucy Raw, Bruce J. Smith
Abstract: A flashcopy of a source storage volume to a target storage volume is initiated. The content of the source storage volume is stored on the target storage volume in a space efficient manner. The space requirement of the stored content on the target storage volume is monitored. The flashcopy is terminated when the space requirement reaches a predetermined level. The stored content on the target storage volume is copied to a backup storage medium. A new flashcopy of the source storage volume is initiated.
Type:
Grant
Filed:
March 22, 2010
Date of Patent:
October 15, 2013
Assignee:
International Business Machines Corporation
Inventors:
Gordon D. Hutchison, Cameron J. McAllister, Lucy Raw, Bruce J. Smith
Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.
Abstract: A system and method are provided for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters. A SoC is provided with an internal hardware-enabled memory speed control logic (MSCL) core. An array of SoC memory control parameter registers is accessed and a set of parameters is selected from one of the registers. The selected set of parameters is delivered to a SoC memory controller, to replace an initial set of parameters, and the memory controller manages an off-SoC memory using the delivered set of parameters.
Abstract: System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner.
Type:
Grant
Filed:
March 22, 2010
Date of Patent:
April 23, 2013
Assignees:
Sony Corporation, Sony Mobile Communications AB
Abstract: A network memory system for ensuring compliance is disclosed. The network memory system comprises a first appliance configured to encrypt first data, store the encrypted first data in a first memory device. The first appliance also determines whether the encrypted first data exists in a second appliance and transmits a store instruction comprising the encrypted first data based on the determination that the encrypted first data does not exist in the second appliance. The second appliance is further configured to receive a retrieve instruction comprising an index at which the encrypted first data is stored, process the retrieve instruction to obtain encrypted response data, and decrypt the encrypted response data.