Patents Examined by Marwan Ayash
  • Patent number: 8370583
    Abstract: A network memory system comprises a first appliance and a second appliance. The first appliance receives data and determines whether a portion of the data is locally accessible to the second appliance. The first appliance generates an instruction based on the determination and transfers the instruction to the second appliance over a communication network. The second appliance receives the instruction from the first appliance over the communication network and processes the instruction to obtain the data. The second appliance then transfers the data to a computer.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: February 5, 2013
    Assignee: Silver Peak Systems, Inc.
    Inventor: David Anthony Hughes
  • Patent number: 8370597
    Abstract: Technologies are described for implementing a migration mechanism in a storage system containing multiple tiers of storage with each tier having different cost and performance parameters. Access statistics can be collected for each territory, or storage entity, within the storage system. Data that is accessed more frequently can be migrated toward higher performance storage tiers while data that is accessed less frequently can be migrated towards lower performance storage tiers. The placement of data may be governed first by the promotion of territories with higher access frequency to higher tiers. Secondly, data migration may be governed by demoting territories to lower tiers to create room for the promotion of more eligible territories from the next lower tier. In instances where space is not available on the next lower tier, further demotion may take place to an even lower tier in order to make space for the first demotion.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: February 5, 2013
    Assignee: American Megatrends, Inc.
    Inventors: Paresh Chatterjee, Ajit Narayanan, Loganathan Ranganathan, Sharon Enoch
  • Patent number: 8359429
    Abstract: System and method for distributing volume status information in a storage system. According to one embodiment, a system may include a plurality of volumes configured to store data, where the volumes are configured as mirrors of one another, and a plurality of hosts configured to access the plurality of volumes. A first one of the plurality of hosts may be configured to execute a mirror recovery process and to maintain a progress indication of the mirror recovery process, and the first host may be further configured to distribute the progress indication to another one or more of the plurality of hosts.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: January 22, 2013
    Assignee: Symantec Operating Corporation
    Inventors: Gopal Sharma, Richard Gorby, Santosh S. Rao, Aseem Asthana
  • Patent number: 8312226
    Abstract: A first appliance of a network memory includes a processor configured to receive data. The processor determines whether the data is locally accessible to a second appliance of the network memory and generates an instruction based on the determination in order that the second appliance obtain the data. The processor then transfers the instruction over a communication network to the second appliance. In another first appliance of a network memory, the first appliance includes a processor configured to receive an instruction over a communication network from a second appliance of the network memory. The processor processes the instruction to determine an action to perform to obtain the data. The processor performs the action to obtain the data if the data is locally accessible to the first appliance.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: November 13, 2012
    Assignee: Silver Peak Systems, Inc.
    Inventor: David Anthony Hughes
  • Patent number: 8271750
    Abstract: A data processing system includes a data store having storage locations storing entries which can be used for a variety of purposes, such as operand value prediction, branch prediction, etc. An entry profile store stores profile data for more candidate entries than there are storage locations within the data store. The profile data is used to determine replacement policy for entries within the data store. The profile data can include hash values used to determine whether predictions associated with candidate entries were correct without having to store the full predictions within the profile data.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: September 18, 2012
    Assignee: ARM Limited
    Inventors: Sami Yehia, Marios Kleanthous
  • Patent number: 8250331
    Abstract: Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: August 21, 2012
    Assignee: Microsoft Corporation
    Inventors: Koichi Yamada, Gad Sheaffer, Ali-Reza Adl-Tabatabai, Landy Wang, Martin Taillefer, Arun Kishan, David Callahan, Jan Gray, Vadim Bassin
  • Patent number: 8250330
    Abstract: A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each entry corresponds to no more than one of the memory modules. The tables support asymmetric population of the memory modules within the ports; each port is capable of having a different number of memory modules relative to the other ports. The tables impose no restrictions on where the memory modules are to be inserted within the ports, both number-wise and position-wise. The tables are independently configurable; the configuration of each table is modifiable independently of the configurations of the other tables. Each table is dynamically configurable. The entries of a table are modifiable to reflect changes in the number and type of the memory modules connected, without restarting or temporarily halting the computer system containing the memory controller.
    Type: Grant
    Filed: December 11, 2004
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Eric N. Lais, Donald R. DeSota, Michael Grassi, Bruce M. Gilbert
  • Patent number: 8209460
    Abstract: A dual-chip package is disclosed which includes at least two memory chips each of which may contain buffer and flash memories having different address systems from each other. Each memory chip may include a register for storing first and second flag signals each indicative of selections of corresponding memory chips, a comparator circuit for comparing the first and second flag signals in the register with a reference signal to generate a flash access signal and a buffer access signal, and a controller for controlling the buffer memory and the flash memory in response to the flash access signal and the buffer access signal.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: June 26, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jin-Yub Lee
  • Patent number: 8200916
    Abstract: A color control node includes an interface for communicating with multiple storage controllers, wherein the storage controllers maintain a primary storage system at a primary site and a secondary storage system at a secondary site; and wherein the storage controllers maintain a current color and associate all writes with the current color without polling the color control node. The color control node also includes operational capability for issuing a polling command to instruct the storage controllers to poll the color control node for the current color prior to associating each write with a new color; receiving an acknowledgment of receipt of the polling command; changing the current color to a new color responsive to receiving the acknowledgment; issuing a storage command to the storage controllers indicating the new color; and instructing each storage controller to cease polling the color control node for the current color.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: Shira Ben Dor, Amir Kredi, Avied Zlotnick, Henry Butterworth
  • Patent number: 8161247
    Abstract: Synchronizing threads on loss of memory access monitoring. Using a processor level instruction included as part of an instruction set architecture for a processor, a read, or write monitor to detect writes, or reads or writes respectively from other agents on a first set of one or more memory locations and a read, or write monitor on a second set of one or more different memory locations are set. A processor level instruction is executed, which causes the processor to suspend executing instructions and optionally to enter a low power mode pending loss of a read or write monitor for the first or second set of one or more memory locations. A conflicting access is detected on the first or second set of one or more memory locations or a timeout is detected. As a result, the method includes resuming execution of instructions.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: April 17, 2012
    Assignee: Microsoft Corporation
    Inventors: Jan Gray, David Callahan, Burton Jordan Smith, Gad Sheaffer, Ali-Reza Adl-Tabatabai, Bratin Saha
  • Patent number: 8140815
    Abstract: This Sampling Object Cache System (“SOCS”) estimates the size of an in-memory heap-based object cache without the need to serialize every object within the cache. SOCS samples objects at a user-determined rate and then computes a “sample size average” for each type of class—whether a top class, type of top class or non top class. Using these sample size averages, a statistically accurate measure of the overall size of the cache is calculated by adding together the total size of the objects in the cache for each class type.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Aaron K Shook, Andrew Ivory, Ching C. A. Chow, Erik J. Burckart, Rohit D. Kelapure
  • Patent number: 8122203
    Abstract: A method, system, and computer program product for implementing Serviceability Level Indicator Processing (SLIPs) for storage alterations in a computer system is provided. A plurality of storage release requests is analyzed to identify an address monitored by a storage alteration slip. Upon identification of the address, the storage alteration slip is disabled and an initialization slip is re-enabled.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Harold Steven Huber, Miguel Angel Perez, David Charles Reed, Max Douglas Smith
  • Patent number: 8095769
    Abstract: A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memo
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: January 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rotem Porat, Moshe Anschel, Itay Peled, Erez Steinberg, Ziv Zamsky
  • Patent number: 8082415
    Abstract: This Sampling Object Cache System (“SOCS”) estimates the size of an in-memory heap-based object cache without the need to serialize every object within the cache. SOCS samples objects at a user-determined rate and then computes a “sample size average” for each type of class—whether a top class, type of top class or non top class. Using these sample size averages, a statistically accurate measure of the overall size of the cache is calculated by adding together the total size of the objects in the cache for each class type.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Aaron Kyle Shook, Andrew Ivory, Ching Chi Andrew Chow, Erik John Burckart, Rohit Dilip Kelapure
  • Patent number: 7962709
    Abstract: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: June 14, 2011
    Assignee: CommVault Systems, Inc.
    Inventor: Vijay H. Agrawal
  • Patent number: 7949827
    Abstract: This invention aims to optimize an entire storage system by equalizing the access counts in appropriate units. When migrating data in pool volumes to equalize the data access counts, which data migration—data migration in units of pages or data migration in units of volumes—is most appropriate is judged based on the information stored in an access information table storing access information, which is the information about the access counts for the data stored in the disk drives and, based on the judgment, data is migrated in units of pages or volumes so that the data access counts are equalized among groups. The data migration is repeated until the data access counts are equalized among the groups.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: May 24, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Taisuke Kurokawa, Toshimichi Kishimoto
  • Patent number: 7913056
    Abstract: A clustered storage array consists of multiple nodes coupled to one or more storage systems. The nodes provide a LUN-device for access by a client. The LUN-device maps to a source logical unit corresponding to areas of storage on the one or more storage systems. A target logical unit corresponds to different areas of storage on the one or more storage systems. The source logical unit is migrated in parallel by the multiple nodes to the target logical unit. Data to be copied from the source logical unit to the target logical unit are grouped into data chunks. Two or more of the plurality of nodes concurrently attempt to acquire an exclusive lock for a set of data chunks. The node acquiring the exclusive lock migrates the set of data chunks from the source logical unit to the target logical unit, while the exclusive lock is used to prevent other nodes from migrating the set of data chunks.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: March 22, 2011
    Assignee: EMC Corporation
    Inventors: Michael F. Brown, Kiran P. Madnani, David W. DesRoches
  • Patent number: 7870355
    Abstract: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: January 11, 2011
    Assignee: CommVault Systems, Inc.
    Inventor: Andrei Erofeev
  • Patent number: 7870332
    Abstract: Various aspects of the invention provide a system and method of operating a data storage drive using any one of one or more data storage devices. In a representative embodiment, a data storage device may be used in a data network and may be referred to as a network attached storage device. Aspects of the invention insure that a data storage drive that that is transferred from a first data storage device to a second data storage device retains the same operational functionality it had when its was operated from the first data storage device.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: January 11, 2011
    Assignee: Broadcom Corporation
    Inventor: Christopher S. Wilson
  • Patent number: 7818513
    Abstract: Transactional memory (TM) may be used in conjunction with various synchronization mechanisms, such as that copy a current version of an object, update the copy, and then cause the copy to become current atomically by changing a “current version” indicator. Software operations to modify an object may first make a private copy of the object, modify the private copy, and atomically make the private copy the current version while verifying that no other software operation or transaction has concurrently updated the object. A transaction may be used to update the current copy of a collection of data “in place” and thereby avoiding the necessity to make a copy of the data being modified. If the transactional memory mechanism is unable to complete the transaction to modify the collection of data in place, a set of software operations may be used to modify the collection of data.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: October 19, 2010
    Assignee: Oracle America, Inc.
    Inventor: Mark S. Moir