Patents Examined by Mary Wilczewski
  • Patent number: 10079181
    Abstract: A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi
  • Patent number: 10074517
    Abstract: A plasma treatment method includes: creating a plasma from a mixed gas containing carbon and nitrogen to generate CN active species, and treating a surface of a semiconductor substrate with the CN active species.
    Type: Grant
    Filed: July 7, 2012
    Date of Patent: September 11, 2018
    Assignee: SONY CORPORATION
    Inventors: Nobuyuki Kuboi, Masanaga Fukusawa
  • Patent number: 10067395
    Abstract: A pixel array includes pixel unit sets each including a substrate having first and second pixel regions, a scan line, first and second data lines extending along a second direction, first and second active devices respectively in the first and second pixel regions, and first and second pixel electrodes respectively located in the first and second pixel regions and electrically connected to the first and second active devices, respectively. The scan line includes a main scan line and first and second branch scan lines (connected to the main scan line) extending along a first direction. The first active device is electrically connected to the first branch scan line and the first data line. The second active device is electrically connected to the second branch scan line and the second data line. At least one of the first and second data lines is overlapped with the first and second pixel electrodes.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: September 4, 2018
    Assignee: Au Optronics Corporation
    Inventors: Chun-Feng Lin, Yao-An Hsieh, Yu-Ping Kuo, Ching-Sheng Cheng
  • Patent number: 10060904
    Abstract: In accordance with the disclosure, a method of forming a nanochannel is provided. The method includes depositing a photosensitive film stack over a substrate; forming a pattern on the film stack using interferometric lithography; depositing a plurality of silica nanoparticles to form a structure over the pattern; removing the pattern while retaining the structure formed by the plurality of silica nanoparticles, wherein the structure comprises one or more enclosed nanochannels, wherein each of the one or more nanochannels comprise one or more sidewalls and a roof; and partially sealing the roof of one or more nanochannels, wherein the roof comprises no more than one unsealed nanochannel per squared micron.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: August 28, 2018
    Assignee: STC.UNM
    Inventors: Steven R. J. Brueck, Yuliya Kuznetsova, Alexander Neumann
  • Patent number: 10062640
    Abstract: Semiconductor devices may include an internal circuit, a sealing region surrounding the internal circuit, and a decoupling capacitor region in the sealing region. The decoupling capacitor region may include decoupling capacitors. Each of the decoupling capacitors may include a first capacitor metal wiring pattern connected to a high power supply line, a second capacitor metal wiring pattern spaced apart from the first capacitor metal wiring pattern and connected to a low power supply line, and a dielectric pattern between the first capacitor metal wiring pattern and the second capacitor metal wiring pattern.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-yong Park, Jeong-hoon Ahn
  • Patent number: 10062630
    Abstract: A semiconductor die includes an III-V semiconductor body having a periphery devoid of active devices, the periphery terminating at an edge face of the semiconductor die. The semiconductor die further includes a seal ring structure above the periphery of the III-V semiconductor body and a barrier. The barrier is disposed over the periphery of the III-V semiconductor body at least between the seal ring structure and the edge face of the semiconductor die. The barrier has a density which prevents water, water ions, sodium ions and potassium ions from diffusing through the barrier.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 28, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 10062602
    Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 28, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS—Centre National de la Recherche Scientifique, APPLIED MATERIALS, Inc
    Inventors: Nicolas Posseme, Sebastien Barnola, Olivier Joubert, Srinivas Nemani, Laurent Vallier
  • Patent number: 10062687
    Abstract: A semiconductor device includes a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, a capacitor on the interlayer dielectric layer, and a PN-junction diode in the semiconductor substrate and below the capacitor. The PN-junction diode includes a p-type ion implanted region and an n-well located below the p-type ion implanted region and completely surrounding the p-type ion implanted region. The PN-junction diode in the semiconductor substrate may prevent noise from entering the capacitor to improve the noise immunity of the semiconductor device.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: August 28, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deng-Ping Yin
  • Patent number: 10056266
    Abstract: A method for manufacturing a resistive device, includes depositing a first electrically conductive layer on a substrate; forming an etching mask on the first conductive layer; etching the first conductive layer through the mask, such as to obtain a plurality of electrically conductive pillars separated from one another; and forming storage elements with variable electrical resistance at the tops of the electrically conductive pillars, such that each storage element is supported by one of the electrically conductive pillars, the step of forming the storage elements including the following operations depositing a first layer by non-collimated cathode sputtering at normal incidence relative to the substrate; and depositing a second layer on the first layer by cathode sputtering, the second layer including a first chemical species sputtered at an oblique incidence.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 21, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), UNIVERSITE GRENOBLE ALPES
    Inventors: Bernard Dieny, Maxime Darnon, Gabriele Navarro, Olivier Joubert
  • Patent number: 10056366
    Abstract: Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10056367
    Abstract: Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10050168
    Abstract: An imaging sensor system includes a pixel array having a plurality of pixel cells disposed in a first semiconductor layer, where each one of the plurality of pixel cells has a single photon avalanche diode (SPAD) disposed proximate to a front side of a first semiconductor layer. Each of the plurality of pixel cells includes a guard ring disposed in the first semiconductor layer in a guard ring region proximate to the SPAD, and also includes a guard ring region reflecting structure disposed in the guard ring region proximate to the guard ring and proximate to the front side of the first semiconductor layer. The imaging sensor system also includes control circuitry coupled to the pixel array to control operation of the pixel array, and readout circuitry coupled to the pixel array to readout image data from the plurality of pixel cells.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 14, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventor: Eric A. G. Webster
  • Patent number: 10047393
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device, the resulting structure, and a method for using the resulting structure. A substrate is provided. A hard mask layer is patterned over at least a portion of the substrate. Regions of the substrate not protected by the hard mask are doped to form a source region and a drain region. The hard mask layer is removed. A dielectric layer is deposited on the substrate. An insulative layer is deposited on the dielectric layer. A nano-channel is created by etching a portion of the insulative layer which passes over the source region and the drain region.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10050025
    Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: August 14, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jonathan Almeria Noquil, Osvaldo Jorge Lopez, Haian Lin
  • Patent number: 10043816
    Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kim Taekyung, Kwang Soo Seol, Seong Soon Cho, Sunghoi Hur, Jintae Kang
  • Patent number: 10030265
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device, the resulting structure, and a method for using the resulting structure. A substrate is provided. A hard mask layer is patterned over at least a portion of the substrate. Regions of the substrate not protected by the hard mask are doped to form a source region and a drain region. The hard mask layer is removed. A dielectric layer is deposited on the substrate. An insulative layer is deposited on the dielectric layer. A nano-channel is created by etching a portion of the insulative layer which passes over the source region and the drain region.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10032885
    Abstract: A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material on the substrate, thereby forming a channel; filling a top portion of the channel with an intermediate implant forming a vertically bi-modal dopant distribution, with one doping concentration peak in the top portion of the channel and another doping concentration peak in the punch through stopper; and patterning fins into the channel and the punch though stopper to form a finFET structure.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gauri Karve, Robert R. Robison, Reinaldo A. Vega
  • Patent number: 10032745
    Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.
    Type: Grant
    Filed: July 26, 2014
    Date of Patent: July 24, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Miyaki, Masaru Yamada
  • Patent number: 10026786
    Abstract: A display device comprising a display region on which a plurality of subpixels are arranged. The plurality of subpixels respectively comprise a transistor, a first organic insulating film, an inorganic insulating film, an electrode, and a second organic insulating film that covers an edge part of a first region in which a pattern of the electrode is formed. The inorganic film comprises an opening in a region that overlaps with the second region in which a pattern of the electrode is not formed in a planar view. The opening is formed in a middle between the first region of a first subpixel and the first region of a second subpixel or at a point located on the side closer to the first subpixel between the first region of the first subpixel and the first region of the second subpixel.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: July 17, 2018
    Assignee: Japan Display Inc.
    Inventors: Ikuo Matsunaga, Kenta Kajiyama
  • Patent number: 10027085
    Abstract: A Q-switched laser includes a laser cavity including a cavity mirror and an output coupler mirror. The Q-switched laser also includes a doped laser gain material disposed in the laser cavity and a Q-switch including a saturable absorber comprising Fe2+:ZnSe or Fe2+:ZnS.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 17, 2018
    Assignee: The UAB Research Foundation
    Inventors: Sergey B. Mirov, Andrew Gallian, Alan Martinez, Vladimir V. Fedorov