Patents Examined by Mary Wilczewski
  • Patent number: 10727339
    Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Gilbert Dewey, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Ravi Pillarisetty, Han Wui Then, Niloy Mukherjee, Sansaptak Dasgupta
  • Patent number: 10720376
    Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: July 21, 2020
    Assignee: Littelfuse, Inc.
    Inventors: Gi-Young Jeun, Kang Rim Choi
  • Patent number: 10720520
    Abstract: A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: July 21, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Seong-Eun Park, Jianwei Wan, Mihir Tungare, Peter Kim, Srinivasan Kannan
  • Patent number: 10714471
    Abstract: A method for fabricating a semiconductor device includes forming a first mask layer, a second mask layer, and a plurality of first patterned layers on an interlayer dielectric layer and a plurality of gate structures. A plurality of first openings separate the first patterned layers with each across a source region, a drain region, and a portion of an isolation area between the source and the drain regions. The second mask layer is then patterned by etching. The method includes forming a plurality of discrete second patterned layers above the isolation areas between source and drain regions and then forming a patterned first mask layer by etching. Further, the method includes forming a plurality of contact vias to expose the source/drain regions through etching using the patterned first mask layer and second mask layer as an etch mask, and then forming a metal silicide layer on each source/drain region.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 14, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manfacturing International (Shanghai) Corporation
    Inventors: Yihua Shen, Yunchu Yu, Jian Pan, Fenghua Fu
  • Patent number: 10714663
    Abstract: A method of manufacturing a light emitting device, includes providing a light emitting element having an element upper surface, an element lower surface opposite to the element upper surface in a thickness direction of the light emitting element, and an element side surface between the element upper surface and the element lower surface. A wavelength converter having a converter lower surface is provided. The wavelength converter is joined to the light emitting element using an adhesive so that the converter lower surface faces the element upper surface. The converter lower surface has an exposed region that does not face the element upper surface viewed along the thickness direction. The adhesive covers the element side surface and the exposed region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 14, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Daisuke Sato, Atsushi Hashizume, Toshiki Nishihama, Shimpei Maeda
  • Patent number: 10714341
    Abstract: Lift-off methods for fabricating metal line patterns on a substrate are provided. For example, a method to fabricate a device includes forming a sacrificial layer on a substrate and forming a photoresist mask over the sacrificial layer, isotropically etching a portion of the sacrificial layer exposed through an opening of the photoresist mask to form an undercut region in the sacrificial layer below the photoresist mask, wherein the undercut region defines an overhang structure, and anisotropically etching a portion of the sacrificial layer exposed through the opening of the photoresist mask to form an opening through the sacrificial layer down to the substrate. Metallic material is deposited to cover the photoresist mask and to at least partially fill the opening formed in the sacrificial layer without coating the overhang structure with metallic material. The sacrificial layer is dissolved to lift-off the metallic material covering the photoresist mask.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: July 14, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Guy M. Cohen, Sebastian U. Engelmann, Steve Holmes, Jyotica V. Patel
  • Patent number: 10707285
    Abstract: A display device includes: a substrate including a curved portion and a flat portion; an insulating layer disposed on the substrate; a first organic light emitting diode disposed on the insulating layer and having a first projection; and a second organic light emitting diode having a second projection, wherein a light emission portion is disposed in the curved portion and the flat portion, the first projection overlaps the light emission portion disposed in the curved portion and is asymmetric in the light emission portion, and the second projection overlaps the light emission portion in the flat portion and is symmetric in the light emission portion.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Won Ju Kwon, Hee Seong Jeong
  • Patent number: 10707129
    Abstract: A processing method of a wafer includes a cut groove forming step of carrying out cutting with a cutting blade along streets from the back surface of the wafer to form cut grooves, a wafer dividing step of irradiating the wafer with a laser beam along the cut grooves and dividing the wafer into individual chips after the cut groove forming step is carried out, and a die bonding layer disposing step of applying a liquid die bonding agent on the back surface of the wafer and curing it to form the chips on which die bonding layers are formed on the back surface. According to the processing method of the present invention, the occurrence of clogging in the cutting blade and generation of a burr or the like in the die bonding layers can be prevented.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 7, 2020
    Assignee: DISCO CORPORATION
    Inventors: Tetsukazu Sugiya, Heidi Lan
  • Patent number: 10707330
    Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Juergen Thees, Peter Baars, Elliot John Smith
  • Patent number: 10707323
    Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yoshikazu Kondo, Shoji Wada, Hiroshi Yamasaki, Masahiro Iwamoto
  • Patent number: 10693068
    Abstract: Provided are an organic light-emitting display apparatus and a method of manufacturing the same. The organic light-emitting display apparatus includes a substrate; lower electrodes, the lower electrodes being on the substrate and spaced apart from one another; a pixel-defining film, the pixel-defining film having portions that cover ends of the lower electrodes; upper electrodes, an upper electrode corresponding to each lower electrode, each upper electrode including a first portion contacting the corresponding lower electrode and a second portion contacting the pixel-defining film; organic functional layers, each including an emission layer, an organic functional layer corresponding to each upper electrode and disposed thereon; and an electrode on the organic functional layers.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 23, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joongu Lee, Yeonhwa Lee, Sehoon Jeong, Jiyoung Choung
  • Patent number: 10680146
    Abstract: A method for manufacturing a light emitting device includes: preparing a wavelength conversion member; preparing a light emitting element comprising a pair of electrodes at a second face side of the light emitting element; forming a light transmissive member, which includes: disposing a liquid resin material on a second main face of the wavelength conversion member, disposing the light emitting element on the liquid resin material such that (i) a first face of the light emitting element is opposed to the second main face of the wavelength converting member, (ii) a portion of a first lateral face of the light emitting element and a portion of a second lateral face of the light emitting element are covered by the liquid resin material, and (iii) a first corner of the light emitting element is exposed from the liquid resin material, and curing the liquid resin material; and forming a covering member.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 9, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Ikuko Baike, Ryo Suzuki
  • Patent number: 10680150
    Abstract: The invention comprises a solid state infrared source and method of use thereof comprising: (1) an electrically conductive film, comprising a semi-transparent material, the semi-transparent material comprising a transmission property of at least forty percent, wherein at least forty percent of internal infrared emissions from the electrically conductive film transmit to an outer surface of the electrically conductive film, wherein the infrared emissions comprise a peak intensity between 3.9 and 6 micrometers; (2) a first silicon nitride layer; and (3) a second silicon nitride layer, the electrically conductive film positioned between the first silicon nitride layer and the second silicon nitride layer, where applying an electric current of less than one Watt through the electrically conductive film raises a temperature of the electrically conductive film to in excess of eight hundred degrees centigrade in less than twenty milliseconds resultant in the infrared emissions.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 9, 2020
    Inventors: Dragan Grubisik, Davorin Babic, Alex Kropachev, Arshey Patadia, Viet Nguyen
  • Patent number: 10672786
    Abstract: The present disclosure provides a semiconductor device comprising: a block separator including a semiconductor film and a multi-layered insulating film, wherein the multi-layered insulating film surrounds the semiconductor film; memory block stacks divided from each other by the block separator, each memory block stack including interlayer insulating films and conductive patterns alternately stacked, wherein the conductive patterns are coupled to memory cells; and channel structures passing through the memory block stacks and electrically coupled to the memory cells.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10665666
    Abstract: A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10665735
    Abstract: A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to ?40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Peter J. Hopper, William French, Paul Mawson, Steven Hunt, Roozbeh Parsa, Martin Fallon, Ann Gabrys, Andrei Papou
  • Patent number: 10665764
    Abstract: A micro lighting device includes a substrate, an isolation layer formed on the substrate, a side-emission micro device, and a switching device. The side-emission micro device includes a first electrode, a second electrode and an emission surface. The side-emission micro device is disposed in a way so that the emission surface is perpendicular or parallel to the surface of the substrate. The switching device includes a first end, a second end coupled to the first electrode, and a control end.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: May 26, 2020
    Assignee: ACER INCORPORATED
    Inventors: Jui-Chieh Hsiang, Chih-Chiang Chen
  • Patent number: 10658183
    Abstract: An impurity-doping apparatus is provided with: a supporting plate which supports a semiconductor substrate; a wall-like block disposed above the supporting plate floating away from the semiconductor substrate, the wall-like block implements a recess inside so as to establish a space for a solution region containing impurity elements, the solution region is localized on an upper surface of the semiconductor substrate, the upper surface being opposite to an bottom surface facing to the supporting plate; and a laser optical system, configured to irradiate a laser beam onto the upper surface of the semiconductor substrate, through the solution region surrounded by the wall-like block, wherein the impurity elements are doped into a part of the semiconductor substrate by irradiation of the laser beam.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: May 19, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa, Masaaki Ogino
  • Patent number: 10658486
    Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacutring Co., Ltd.
    Inventors: Yi-Jyun Huang, Bao-Ru Young, Tung-Heng Hsieh
  • Patent number: 10651126
    Abstract: A wafer-level bridge die is affixed with an adhesive layer to a redistribution layer (RDL) that has been temporarily bonded to a carrier. Electrical interconnects are formed on the RDL and on the bridge die and encapsulated in a first mold layer. A plurality of dies are coupled to the RDL and the bridge die such that a die is electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die. A second mold layer is formed on the first mold layer to encapsulate the plurality of dies. The temporary bond is then broken and the carrier is removed, exposing the RDL connections.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 12, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Kang Hsiung, Arvind Sundarrajan