Patents Examined by Mary Wilczewski
  • Patent number: 10027085
    Abstract: A Q-switched laser includes a laser cavity including a cavity mirror and an output coupler mirror. The Q-switched laser also includes a doped laser gain material disposed in the laser cavity and a Q-switch including a saturable absorber comprising Fe2+:ZnSe or Fe2+:ZnS.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 17, 2018
    Assignee: The UAB Research Foundation
    Inventors: Sergey B. Mirov, Andrew Gallian, Alan Martinez, Vladimir V. Fedorov
  • Patent number: 10026786
    Abstract: A display device comprising a display region on which a plurality of subpixels are arranged. The plurality of subpixels respectively comprise a transistor, a first organic insulating film, an inorganic insulating film, an electrode, and a second organic insulating film that covers an edge part of a first region in which a pattern of the electrode is formed. The inorganic film comprises an opening in a region that overlaps with the second region in which a pattern of the electrode is not formed in a planar view. The opening is formed in a middle between the first region of a first subpixel and the first region of a second subpixel or at a point located on the side closer to the first subpixel between the first region of the first subpixel and the first region of the second subpixel.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: July 17, 2018
    Assignee: Japan Display Inc.
    Inventors: Ikuo Matsunaga, Kenta Kajiyama
  • Patent number: 10020417
    Abstract: A PV module is formed having an array of PV cells, where the cells are separated by gaps. Each cell contains an array of small silicon sphere diodes (10-300 microns in diameter) connected in parallel. The diodes and conductor layers may be patterned by printing. A continuous metal substrate supports the diodes and conductor layers in all the cells. A dielectric substrate is laminated to the metal substrate. Trenches are then formed by laser ablation around the cells to sever the metal substrate to form electrically isolated PV cells. A metallization step is then performed to connect the cells in series to increase the voltage output of the PV module. An electrically isolated bypass diode for each cell is also formed by the trenching step. The metallization step connects the bypass diode and its associated cell in a reverse-parallel relationship.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: July 10, 2018
    Assignee: Printed Energy Pty Ltd
    Inventors: Tricia Youngbull, Bradley Steven Oraw, William Johnstone Ray
  • Patent number: 10020432
    Abstract: Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. In particular embodiments, the trenches extend into the carrier substrate. In further particular embodiments, the dies are at least partially encapsulated in a dielectric material.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Scott D. Schellhammer, Jeremy S. Frei
  • Patent number: 10020364
    Abstract: One embodiment includes: forming a laminated body by alternately laminating a conducting layer and an interlayer insulating layer on a substrate; forming a memory hole passing through the laminated body; forming a memory gate insulating layer including a charge storage layer on an inner wall of the memory hole; forming a first semiconductor layer on the memory gate insulating layer; forming a cover film on the first semiconductor layer; removing the memory gate insulating layer, the first semiconductor layer, and the cover film on a bottom surface of the memory hole, to expose the substrate; forming an epitaxial layer on the exposed substrate; removing the cover film; and forming the second semiconductor layer along the first semiconductor layer, to electrically couple: the substrate to the first semiconductor layer; and the substrate to the second semiconductor layer, via the epitaxial layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Yamasaki, Makoto Fujiwara, Shinji Mori
  • Patent number: 10014225
    Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming a silicon-nitride layer (SiN) over a dummy gate at a second metal gate type transistor region (e.g. NMOS) avoid dummy gate loss during a CMP process for a PMOS gate. The method can comprise after performing a patterning process to remove hard masks at PMOS and NMOS regions, forming a SiN layer over the NMOS region; performing a patterning process to open the PMOS region and filling gate materials in the PMOS region; performing a CMP to polish a top surface of PMOS such that the polishing stops at SiN. In this way, dummy gate loss can be reduced during the first aluminum CMP step and thus can reduce initial height of dummy gate as compared to the convention method, and improve the filling process of the dummy gate as compared to the conventional method.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 3, 2018
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Yu Bao
  • Patent number: 10014250
    Abstract: A semiconductor device includes a substrate and at least one inductor on the substrate. The inductor includes top portions separated from one another, bottom portions separated from one another, and side portions separated from one other. Each side portion extends between one of the top portions and one of the bottom portions. A semiconductor device includes a substrate, a first patterned conductive layer on the substrate, a second patterned conductive layer, and at least one dielectric layer between the first patterned conductive layer and the second patterned conductive layer. The first patterned conductive layer defines bottom crossbars separated from each other, each bottom crossbar including a bend angle. The second patterned conductive layer defines top crossbars separated from each other, wherein each top crossbar is electrically connected to a bottom crossbar.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: July 3, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Chi Hsieh, Chih-Pin Hung
  • Patent number: 10014442
    Abstract: A vertical type light emitting diode includes a nitride semiconductor having a p-n conjunction structure with a transparent material layer formed on a p type clad layer, the transparent material layer having a refractive index different from that of the p type clad layer and having a pattern structure of mesh, punched plate, or one-dimensional grid form, etc. A reflective metal electrode layer is formed on the transparent material layer as a p-electrode. A stereoscopic pattern is formed in the transparent material layer and the p-electrode deposited, and thereby forming the pattern in the p-electrode. Depositing the p-electrode on only 10 to 70% of the upper portion of the p type clad layer in an ultraviolet ray light emitting diode such that an area where the p type clad layer is exposed is wide increases the transmittance of ultraviolet rays through an area where the p-electrode is not deposited.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 3, 2018
    Assignee: Korea Polytechnic University Industry Academic Cooperation Foundation
    Inventors: Kyoung Kook Kim, Se Mi Oh
  • Patent number: 10008541
    Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Patent number: 10008531
    Abstract: An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first region, and a second isolation trench is formed in the second region. A first liner layer is formed in the first isolation trench, and a second liner layer is formed in the second isolation trench. The second liner layer has a physical characteristic that is different from a corresponding physical characteristic of the first liner layer. An implantation procedure is performed on the second isolation trench and the second liner layer formed therein. The physical characteristic of the second liner layer may be selected to enhance an implantation depth or an implantation uniformity compared to the first liner layer.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: June 26, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Chou, Chia-Shiung Tsai, Feng-Chi Hung, Jiech-Fun Lu, Min-Feng Kao, Shih Pei Chou, Yeur-Luen Tu
  • Patent number: 10002990
    Abstract: A light-emitting device may include a semiconductor body having a first conductivity type, with a front side and a back side. The light-emitting device may also include a porous-silicon region which extends in the semiconductor body at the front side, and a cathode region in direct lateral contact with the porous-silicon region. The light-emitting device may further include a barrier region of electrically insulating material, which extends in direct contact with the cathode region at the bottom side of the cathode region so that, in use, an electric current flows in the semiconductor body through lateral portions of the cathode region.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 19, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Morelli, Fabrizio Fausto Renzo Toia, Giuseppe Barillaro, Marco Sambi
  • Patent number: 10002775
    Abstract: In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 19, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuhei Sato, Keiji Sato, Tetsunori Maruyama, Junichi Koezuka
  • Patent number: 9999129
    Abstract: A microelectronic device comprises a first substrate (110) having a first electrically conductive path (111) therein and a second substrate (120) above the first substrate and having a second electrically conductive path (121) therein, wherein the first electrically conductive path and the second electrically conductive path are electrically connected to each other and form a portion of a current loop (131) of an inductor (130).
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: John S. Guzek, Mihir K. Roy, Brent M. Roberts
  • Patent number: 9985192
    Abstract: A light-emitting diode is provided. The light-emitting diode includes a first semiconductor structure having an upper surface and a lower surface; a second semiconductor layer disposed adjacent to the upper surface; a third semiconductor layer disposed adjacent to the lower surface; two light-emitting layers disposed between the upper surface and the second semiconductor layer and disposed between the lower surface and the third semiconductor layer, respectively; a first electrode disposed over the second semiconductor layer; and a second electrode disposed over the third semiconductor layer.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: May 29, 2018
    Assignee: INNOLUX CORPORATION
    Inventors: Jen-Chieh Peng, Bo-Feng Chen, Tsau-Hua Hsieh
  • Patent number: 9981339
    Abstract: A wafer having an off angle ? is produced from a hexagonal single crystal ingot having an upper surface, a c-plane exposed to the upper surface, and a c-axis perpendicular to the c-plane. The ingot is supported by a wedge member having a wedge angle ? equal to the off angle ?, thereby inclining the upper surface of the ingot by the off angle ? with respect to a horizontal plane. A modified layer is formed by setting the focal point of a laser beam inside the ingot and next applying it to the upper surface, thereby linearly forming a modified layer inside the ingot and cracks extending from the modified layer along the c-plane. The focal point is moved in the second direction to index the focal point by a predetermined amount.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 29, 2018
    Assignee: DISCO CORPORATION
    Inventor: Kazuya Hirata
  • Patent number: 9981844
    Abstract: A source material, which is based on a glass, is arranged on a working surface of a mold substrate. The mold substrate is made of a single-crystalline material. A cavity is formed in the working surface. The source material is pressed against the mold substrate. During pressing a temperature of the source material and a force exerted on the source material are controlled to fluidify source material. The fluidified source material flows into the cavity. Re-solidified source material forms a glass piece with a protrusion extending into the cavity. After re-solidifying, the glass piece may be bonded to the mold substrate. On the glass piece, protrusions and cavities can be formed with slope angles less than 80 degrees, with different slope angles, with different depths and widths of 10 micrometers and more.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: May 29, 2018
    Assignee: Infineon Technologies AG
    Inventors: Alexander Breymesser, Andre Brockmeier, Carsten von Koblinski, Francisco Javier Santos Rodriguez
  • Patent number: 9972506
    Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: May 15, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Donald C. Abbott
  • Patent number: 9972500
    Abstract: The present invention is provided to improve quality or manufacturing throughput of a semiconductor device. A method includes supplying a source gas to a substrate in a process chamber; exhausting an inside of the process chamber; supplying a reaction gas to the substrate; and exhausting the inside of the process chamber, wherein the source gas and/or the reaction gas is supplied in temporally separated pulses in the supply of the source gas and/or in the supply of the reaction gas. Then, the source gas and/or the reaction gas is supplied in temporally separated pulses to form a film during a gas supply time determined by a concentration distribution of by-products formed on a surface of the substrate.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 15, 2018
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Yukinao Kaga, Arito Ogawa, Atsuro Seino, Atsuhiko Ashitani, Ryohei Maeno, Masanori Sakai
  • Patent number: 9966296
    Abstract: The present invention proposes variations of the laser separation method allowing separating homoepitaxial films from the substrates made from the same crystalline material as the epitaxial film. This new method of laser separation is based on using the selective doping of the substrate and epitaxial film with fine donor and acceptor impurities. In selective doping, concentration of free carries in the epitaxial film and substrate may essentially differ and this can lead to strong difference between the light absorption factors in the infrared region near the residual beams region where free carriers and phonon-plasmon interaction of the optical phonons with free carriers make an essential contribution to infrared absorption of the optical phonons. With the appropriate selection of the doping levels and frequency of infrared laser radiation, it is possible to achieve that laser radiation is absorbed in general in the region of strong doping near the interface substrate-homoepitaxial film.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: May 8, 2018
    Inventors: Yury Georgievich Shreter, Yury Toomasovich Rebane, Aleksey Vladimirovich Mironov
  • Patent number: 9960116
    Abstract: A resistor whose characteristic value can be changed without requiring a photolithography process again is provided. The resistor includes a plurality of first resistor units which is connected serially to each other and a second resistor unit which is connected in parallel to part of the first resistor units. Then, after the measurement of a semiconductor integrated circuit, the second resistor unit is electrically disconnected as necessary. The first resistor units may be either a unit including a single resistor or may be a unit including a plurality of resistors.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: May 1, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuaki Ohshima