Patents Examined by Mary Wilczewski
  • Patent number: 11456348
    Abstract: A display device includes a substrate, a pixel, an encapsulation film, a sensing electrode, a pad, a connection wire, and an extension pattern. The substrate include a display area, a non-display area outside the display area, an additional area at a side of the non-display area, and a bending area defined in at least a portion of the additional area. The pixel is on the display area. The encapsulation film is on the pixel. The sensing electrode is on the encapsulation film. The pad is on the additional area. The connection wire is on the non-display area and is directly connected to the sensing electrode. The extension pattern directly connects the pad and the connection wire to each other. The extension pattern traverses the bending area.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: September 27, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki Ho Bang, Eun Hye Kim, Eun Ae Jung, Won Suk Choi
  • Patent number: 11444118
    Abstract: A method of manufacturing an optoelectronic device, including: a) transferring, onto a connection surface of a control circuit, an active diode stack including at least first and second semiconductor layers of opposite conductivity types, so that the second semiconductor layer in the stack faces the connection surface of the control circuit and is separated from the connection surface of the control circuit by at least one insulating layer; b) forming in the active stack trenches delimiting a plurality of diodes, the trenches extending through the insulating layer and emerging onto the connection surface of the control circuit; and c) forming in the trenches metallizations connecting the second semiconductor layer to the connection surface of the control circuit.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 13, 2022
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hubert Bono, Julia Simon
  • Patent number: 11443971
    Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: September 13, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11437597
    Abstract: An organic electroluminescence device includes a first electrode, a hole transport region disposed on the first electrode, a first emission layer disposed on the hole transport region and including a first light-emitting host and a first light-emitting dopant, a second emission layer disposed on the first emission layer and including a first electron transport material and a second light-emitting dopant, an electron transport region disposed on the second emission layer and including a second electron transport material, and a second electrode disposed on the electron transport region, wherein a triplet energy of the first light-emitting host (T1a), a triplet energy of the second light-emitting dopant (T1b) and a triplet energy of the second electron transport material (T1c) satisfy a relation of T1a<T1b<T1c. High emission efficiency may be shown.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 6, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-O Lim, Seunggak Yang, Samil Kho
  • Patent number: 11430676
    Abstract: A semiconductor wafer is heated by a flash of light emitted from a flash lamp after being preheated by a halogen lamp. Temperature of the semiconductor wafer immediately before the flash of light is emitted is measured by a lower radiation thermometer. At the time of irradiation with a flash of light, an upper radiation thermometer measures temperature increase of a front surface of the semiconductor wafer. Front surface temperature of the semiconductor wafer is calculated by adding the temperature increase of the front surface of the semiconductor wafer at the time of irradiation with a flash of light measured by the upper radiation thermometer to the back surface temperature of the semiconductor wafer measured by the lower radiation thermometer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: August 30, 2022
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Hikaru Kawarazaki, Yoshihide Nozaki
  • Patent number: 11417551
    Abstract: High bandwidth time-and-space resolved phase transition microscopy systems configured to detect melt onset in a wafer being processed by laser annealing systems with ultra-short dwell times and spot size.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 16, 2022
    Assignee: Veeco Instruments Inc.
    Inventor: Matthew Earl Wallace Reed
  • Patent number: 11410872
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to oxidized cavity structures within and under semiconductor devices and methods of manufacture. The structure includes: a substrate material; active devices over the substrate material; an oxidized trench structure extending into the substrate and surrounding the active devices; and one or more oxidized cavity structures extending from the oxidized trench structure and formed in the substrate material under the active devices.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 9, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, Steven M. Shank, John J. Ellis-Monaghan, Anthony K. Stamper
  • Patent number: 11404614
    Abstract: Provided is a light-emitting device having a plurality of light-emitting elements with high operation stability and light extraction efficiency. The light-emitting device includes: a light-emitting element; a translucent member which is disposed on the light-emitting element and has a columnar first portion having a bottom surface opposed to an upper surface of the light-emitting element, a second portion formed continuously with the first portion on the first portion and narrowed upward, and a columnar third portion formed continuously with the second portion on the second portion; and a reflective member configured to cover the side surfaces of the translucent member. In this light-emitting device, the height of the first portion of the translucent member in a direction perpendicular to the bottom surface thereof is ? or more the height of the translucent member in the direction perpendicular to the bottom surface.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: August 2, 2022
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Kyotaro Koike, Ji-Hao Liang, Mitsunori Harada, Kaori Tachibana, Shunya Ide, Hiroshi Kotani, Satoshi Ando
  • Patent number: 11404284
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 2, 2022
    Inventors: Yen-Ting Chen, I-Hsieh Wong, Chee-Wee Liu
  • Patent number: 11398559
    Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Jyun Huang, Bao-Ru Young, Tung-Heng Hsieh
  • Patent number: 11398496
    Abstract: A three-dimensional memory device includes an alternating stack of word lines and at least one insulating layers or air gaps located over a substrate, a memory opening fill structure extending through the alternating stack. The memory opening fill structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The word lines are thicker than the insulating layers or air gaps.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: July 26, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Senaka Kanakamedala, Johann Alsmeier
  • Patent number: 11393784
    Abstract: A method for forming semiconductor devices includes attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices. The method further includes forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Alexander Breymesser, Andre Brockmeier, Carsten von Koblinski, Francisco Javier Santos Rodriguez, Ronny Kern
  • Patent number: 11387182
    Abstract: The module structure includes a substrate, a passive element, metal columns and a chip. The passive element, the metal columns and the chip are located on a same side of the substrate. The passive element is located between the substrate and the film where the metal columns and the chip are located. The following applies: the vertical projection of the chip on the substrate overlaps a line segment or closed figure formed by endpoints constituted by the vertical projections of the metal columns on the substrate; the vertical projection of the passive element on the substrate overlaps the line segment or closed figure formed by the endpoints constituted by the vertical projections of the metal columns on the substrate; or the vertical projection of the passive element on the substrate overlaps the vertical projection of the chip on the substrate.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 12, 2022
    Assignee: ANHUI ANUKI TECHNOLOGIES CO., LTD.
    Inventors: Chengjie Zuo, Jun He
  • Patent number: 11387355
    Abstract: A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: July 12, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Seong-Eun Park, Jianwei Wan, Mihir Tungare, Peter Kim, Srinivasan Kannan
  • Patent number: 11387116
    Abstract: In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 12, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuhei Sato, Keiji Sato, Tetsunori Maruyama, Junichi Koezuka
  • Patent number: 11387162
    Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: July 12, 2022
    Assignee: Littelfuse, Inc.
    Inventors: Gi-Young Jeun, Kang Rim Choi
  • Patent number: 11387232
    Abstract: A semiconductor device includes a substrate; a first gate stack disposed on the substrate; a second gate stack disposed on the substrate, wherein a metal component of the first gate stack is different from a metal component of the second gate stack; and a dielectric structure disposed over the substrate and between the first gate stack and the second gate stack, in which the dielectric structure is separated from the first gate stack and the second gate stack, and a distance between the dielectric structure and the first gate stack is substantially equal to a distance between the dielectric structure and the second gate stack.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han Wu, Chie-Iuan Lin, Kuei-Ming Chang, Rei-Jay Hsieh
  • Patent number: 11367654
    Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: June 21, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Karl Mayer, Evelyn Napetschnig, Michael Pinczolits, Michael Sternad, Michael Roesner
  • Patent number: 11362100
    Abstract: Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: June 14, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Feng Zhou, Xian Liu, Steven Lemke, Hieu Van Tran, Nhan Do
  • Patent number: 11355564
    Abstract: An OLED device includes: a first substrate having a bonding surface; a second substrate having a first surface; a coloring unit including an OLED layer and optionally a color-transformation layer, the OLED layer being formed on a selected one of the first and second substrates, the color-transformation layer being formed on the second substrate; and a pixel circuit with TFT functions disposed on the first substrate and coupled to the OLED layer. The bonding surface of the first substrate and the first surface of the second substrate are in direct bonding.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: June 7, 2022
    Assignee: AROLLTECH CO., LTD.
    Inventors: Yih Chang, Yusheng Chang, Tsung Jen Kuo