Abstract: A vertical memory device includes a plurality of memory blocks having a plurality of horizontal gate electrodes spaced apart from each other in a first direction and extending in a second direction. A plurality of vertical channels extends through the horizontal gate electrodes in the first direction. A plurality of charge storage structures are disposed between the vertical channels and the horizontal gate electrodes. A conductive path extends in a third direction. The plurality of memory blocks are arranged in the third direction and are divided from each other by a first division pattern that extends in the second direction. The plurality of horizontal gate electrodes at each level are connected to the conductive path at a first lateral side in the second direction to form a shared memory block.

Abstract: A display apparatus is provided. The display apparatus includes a display panel having a display portion in a display region, a connecting portion, and a bending portion; a cover window on a first side of the display portion, wherein the bending portion connects the display portion and the connecting portion; a support layer between the display portion and the connecting portion; a first back film covering a back surface of the connecting portion, the first back film on a side of the connecting portion closer to the display portion; a first adhesive layer attaching the support layer to the first back film; a metal plate between the support layer and the display portion; and a second adhesive layer attaching the support layer to the metal plate. The display apparatus includes a stress-reducing space. The stress-reducing space is open to a bending cavity that is partially surrounded by the bending portion.

Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

Abstract: A semiconductor storage device includes a stacked body, a first columnar portion, a second columnar portion, and second insulating layers. The stacked body includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked in a first direction. The first columnar portion being in a first region, and the second columnar portion being in a second region. The first columnar penetrates the stacked body in the first direction and includes a semiconductor layer. The second columnar portion penetrates the stacked body in the first direction and includes an insulating layer thereon. The second insulating layers are between the second columnar portion and either the conductive layers or the first insulating layers. The insulating layer on the second columnar portion. The second insulating layers are between the insulating layer on the second columnar portion and one of the conductive layers or the first insulating layers.

Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Abstract: A semiconductor chip includes a chip body including a signal input/output circuit, a chip pad structure disposed on a surface of the chip body, the chip pad structure including first and second chip pads, the two chip pads having different surface areas, and a chip pad selection circuit disposed in the chip body and electrically connected to the signal input/output circuit and the chip pad structure. The chip pad selection circuit is configured to selectively and electrically connect one of the first and second chip pads to the signal input/output circuit.

Abstract: A semiconductor device includes a line; a source structure on the line; a stack structure on the source structure; a first slit structure penetrating the stack structure; a second slit structure penetrating the stack structure; and a contact plug adjacent to the first slit structure in a first direction. The first slit structure and the second slit structure may be spaced apart from each other by a first distance in a second direction that is perpendicular to the first direction. The contact plug penetrates the source structure, the contact plug being electrically connected to the lower line. The first slit structure and the contact plug may be spaced apart from each other by a second distance in the first direction, and the second distance may be longer than the first distance.

Abstract: A semiconductor device comprises a substrate; an element isolation film that defines a first active region in the substrate; a first gate electrode on the first active region; a first source/drain region located inside the first active region between the element isolation film and the first gate electrode; and an isolation contact that extends in a vertical direction intersecting an upper face of the substrate, in the element isolation film. The isolation contact is configured to have a voltage applied thereto.

Abstract: A vertical type non-volatile memory device includes a substrate having a cell array area of a block unit and an extension area, a vertical contact disposed in the extension area, a plurality of vertical channel structures provided on the substrate in the cell array area, a plurality of dummy channel structures provided on the substrate in the extension area, and a plurality of gate electrode layers and a plurality of interlayer insulation layers stacked alternately on the substrate. In an electrode pad connected to the vertical contact, dummy channel structures are disposed at both sides of the vertical contact and a horizontal cross-sectional surface of each of the plurality of dummy channel structures has a shape which is longer in one direction.

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.

Abstract: A light-emitting device includes, light-emitting elements each including a first electrode, a second electrode, and a quantum dot layer interposed between the first electrode and the second electrode. The quantum dot layer includes a quantum dot structure including a quantum dot having a core and a first shell, with which the core is coated, and a second shell, with which the first shell is coated. The first shell and the second shell have a crystal structure, and at least one set of the quantum dots adjacent to each other is connected to each other by the crystal structure of the second shell. Forming the quantum dot layer includes vaporizing a solvent of a solution in which a ligand is dispersed, cooling, and forming the second shell by epitaxial growth around the first shell in that order.

Abstract: Provided is display substrate, including driving circuit board, and first electrode layer, insulating layer, second electrode layer, isolation layer, transparent conductive layer sequentially stacked thereon. Driving circuit board includes pixel and bonding regions. First electrode layer includes first sub-portion in bonding region and second sub-portion in pixel region. Insulating and isolation layers are partially cover bonding and pixel regions. Insulating layer has first via hole in area corresponding to first sub-portion. Isolation layer has second via hole in the area. Axes of first and second via holes coincide, first sub-portion is exposed at first and second via holes. Second electrode layer is in pixel region, coupled to second sub-portion through third via hole in area corresponding to second sub-portion. Isolation layer has fourth via hole in area corresponding to second electrode layer. Transparent conductive layer is in pixel region, coupled to second electrode layer through fourth via hole.

Abstract: A semiconductor memory structure includes a substrate, a bit line disposed on the substrate, a dielectric liner disposed on a side of the bit line, and a capacitor contact and a filler disposed on the substrate. The bit line extends in a first direction. The dielectric liner includes a first nitride liner disposed on a sidewall of the bit line, an oxide liner disposed on a sidewall of the first nitride liner, and a second nitride liner disposed on a sidewall of the oxide liner. In a second direction perpendicular to the first direction, the capacitor contact is spaced apart from the bit line by the first nitride liner, the oxide liner, and the second nitride liner, and the width of the filler is greater than the width of the capacitor contact. A method for forming the semiconductor memory structure is also provided.

Abstract: An organic light emitting diode display is provided. The organic light emitting diode display comprises an organic light emitting diode panel, a quarter-wavelength retarder disposed on the organic light emitting diode panel, a polarizer disposed on the quarter-wavelength retarder, an adhesive layer disposed on the polarizer and a diffraction grating film adhered to the polarizer by the adhesive layer. The diffraction grating film comprises a substrate and a first diffraction grating layer comprising a plurality of first gratings aligned with a first direction disposed on the substrate.

Abstract: Described herein is a technique capable of forming a film whose characteristics are uniform by discharging a residual component from a plurality of grooves before supplying a process gas. According to one aspect thereof, there is provided a substrate processing apparatus including: (a) loading a substrate on which a plurality of grooves are provided into a process chamber, wherein a residue is adhered to the plurality of the grooves; (b) desorbing the residue from the plurality of the grooves by heating the substrate; and (c) discharging the residue from the plurality of the grooves to a process space of the process chamber after (b) is performed by heating a surface of the substrate to a temperature higher than a temperature of the substrate in (b).

Abstract: Embodiments of the present application relate to the field of semiconductor manufacturing technologies, in particular to a semiconductor structure and a mask plate structure. The semiconductor structure includes a substrate, where the substrate is provided therein with active areas and a plurality of bit line structures arranged at intervals in parallel in the substrate. A plurality of word line structures are arranged at intervals in parallel in the substrate. The word line structures and the bit line structures intersect to define a plurality of grids arranged in an array on the substrate. Capacitor plugs are located in the grids. Projection of each of the capacitor plugs on the substrate covers a part of one of the active areas. Cross sections of the capacitor plugs are arcuate in a cross section parallel to a surface of the substrate.

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, a layer stack, memory cells, a semiconductor layer, a contact structure, and gate line slit structures. The substrate includes a doped region. The layer stack is formed over the substrate. The memory cells are formed through the layer stack over the substrate. The semiconductor layer is formed on the doped region and a side portion of a channel layer that extends through the layer stack. The contact structure electrically contacts the doped region. A dielectric material is filled in the gate line slit structures. Air gaps are formed in the gate line slit structures by the dielectric material.