Patents Examined by Mary Wilczewski
  • Patent number: 10153382
    Abstract: A mechanical memory transistor includes a substrate having formed thereon a source region and a drain region. An oxide is formed upon a portion of the source region and upon a portion of the drain region. A pull up electrode is positioned above the substrate such that a gap is formed between the pull up electrode and the substrate. A movable gate has a first position and a second position. The movable gate is located in the gap between the pull up electrode and the substrate. The movable gate is in contact with the pull up electrode when the movable gate is in a first position and is in contact with the oxide to form a gate region when the movable gate is in the second position. The movable gate, in conjunction with the source region and the drain region and when the movable gate is in the second position, form a transistor that can be utilized as a non-volatile memory element.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: December 11, 2018
    Assignee: Massachusetts Institute of Technology
    Inventor: Carl O. Bozler
  • Patent number: 10153219
    Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-jun Jeon, Nae-in Lee, Byung-Iyul Park
  • Patent number: 10147497
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Livio Baldi, Marcello Mariani
  • Patent number: 10147735
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tadashi Iguchi, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Patent number: 10141407
    Abstract: According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: David Seo, Ho-jung Kim, In-kyeong Yoo, Myoung-jae Lee, Seong-ho Cho
  • Patent number: 10135029
    Abstract: A display device includes: a light emitting element including a light emitting layer, and a first electrode and a second electrode that hold the light emitting layer therebetween; and a sealing layer on the light emitting element, wherein the sealing layer includes an organic layer, and a first inorganic layer and a second inorganic layer that hold the organic layer from an upper side and a lower side. A peripheral part of the first inorganic layer and a peripheral part of the second inorganic layer are connected around an outer perimeter of the organic layer and vertically overlap with each other so as not to cover an edge surface of each other's from a lateral side. At least one of the first inorganic layer and the second inorganic layer is an Aluminum Oxide film.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 20, 2018
    Assignee: Japan Display Inc.
    Inventor: Akinori Kamiya
  • Patent number: 10134821
    Abstract: A thin film transistor (TFT) substrate having reduced differences in heights in areas thereof so as to facilitate subsequent processing is disclosed. In one aspect, the TFT substrate includes a substrate having a first area in which a TFT is not disposed and a second area in which a TFT is disposed, a height adjustment layer disposed on the substrate in an area corresponding to at least a part of the first area. The TFT substrate also includes a TFT disposed on the substrate in an area corresponding to the second area.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Dong-Won Lee
  • Patent number: 10121655
    Abstract: Plasma source assemblies comprising a housing with an RF hot electrode and a return electrode are described. The housing includes a gas inlet and a front face defining a flow path. The RF hot electrode includes a first surface oriented substantially parallel to the flow path. The return electrode includes a first surface oriented substantially parallel to the flow path and spaced from the first surface of the RF hot electrode to form a gap. Processing chambers incorporating the plasma source assemblies and methods of using the plasma source assemblies are also described.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: November 6, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Anantha K. Subramani, Kaushal Gangakhedkar, Abhishek Chowdhury, John C. Forster, Nattaworn Nuntaworanuch, Kallol Bera, Philip A. Kraus, Farzad Houshmand
  • Patent number: 10121905
    Abstract: Provided is a semiconductor device including a transistor in which a first gate and a second gate are provided with a channel formation region provided therebetween and which achieves both control of the threshold voltage and an increase in the on-state current. In a period during which first voltage with which the transistor is turned off is supplied to the first gate, control voltage for controlling the threshold voltage is supplied to the second gate. In a period during which second voltage with which the transistor is turned on is supplied to the first gate, the second voltage is supplied to the first gate and voltage in which voltage based on change in the voltage of a signal supplied to the first gate is added to the control voltage is supplied to the second gate.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: November 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroyuki Miyake
  • Patent number: 10115622
    Abstract: A wafer processing laminate including support, temporary adhesive material layer laminated on the support, and wafer stacked on temporary adhesive material layer, wafer having front surface on which circuit is formed and back surface to be processed, temporary adhesive material layer including first temporary adhesive layer composed of thermoplastic resin layer (A) laminated on front surface of wafer and second temporary adhesive layer composed of thermosetting resin layer (B) laminated on first temporary adhesive layer, thermoplastic resin layer (A) being soluble in cleaning liquid (D) after processing wafer, thermosetting resin layer (B) being insoluble in cleaning liquid (D) after heat curing and capable of absorbing cleaning liquid (D) such that cleaning liquid (D) permeates into layer (B). This wafer processing laminate allows a wide selection of materials, facilitates separation and collection of processed wafer, meets requirements on various processes, and can increase productivity of thin wafers.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: October 30, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shohei Tagami, Michihiro Sugo, Hideto Kato
  • Patent number: 10109701
    Abstract: An organic EL display device includes: a lower electrode; an upper electrode; a first organic layer which is disposed between the lower electrode and the upper electrode and is formed of a plurality of layers including a light emitting layer formed of an organic material that emits light; a metal wire that extends between the pixels within the display region; and a second organic layer which is formed of a plurality of layers the same as that of the first organic layer and which comes into contact with a part of the metal wire and does not come into contact with the first organic layer. The upper electrode comes into contact with the metal wire in the periphery of the second organic layer. Accordingly, it is possible to uniformize the potential of the upper electrode without reducing the light emission area.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: October 23, 2018
    Assignee: Japan Display Inc.
    Inventors: Yuko Matsumoto, Toshihiro Sato
  • Patent number: 10109709
    Abstract: A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi
  • Patent number: 10103332
    Abstract: A method of manufacturing an evaporation mask, includes preparing a semi-finished body of an evaporation mask including a reinforcing bar and a film having an area larger than an area of the reinforcing bar, forming an opening pattern in a region, which is prevented from planarly overlapping with the reinforcing bar, of the film, and forming at least one projecting portion in a region, which is on a surface opposite to the reinforcing bar and which planarly overlaps with the reinforcing bar, of the film.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: October 16, 2018
    Assignee: Japan Display Inc.
    Inventor: Takeshi Okawara
  • Patent number: 10102907
    Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Chen-Bin Lin, Chi-Fa Ku, Shao-Hui Wu
  • Patent number: 10084013
    Abstract: A thin-film transistor includes a substrate, a gate electrode formed on a surface of the substrate, a gate protection layer and a semiconductor layer stacked on the gate electrode, and an etch stop layer, source terminal metal, and drain terminal metal formed on a surface of the semiconductor layer in such a way that the source terminal metal and the drain terminal metal are respectively located on two opposite sides of the etch stop layer. The thin-film transistor further includes a light shielding layer, an insulation medium layer, and a pixel electrode. The light shielding layer is stacked on the etch stop layer to prevent light from irradiating the semiconductor layer. The insulation medium layer covers the source terminal metal, the drain terminal metal, and the light shielding layer. The pixel electrode is formed on a surface of the insulation medium layer and electrically connected to the drain terminal metal.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: September 25, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Qiuping Huang
  • Patent number: 10084063
    Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Yi-Han Wang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 10083954
    Abstract: A semiconductor device may be provided. The semiconductor device may include a first guard ring disposed in a first region, and a second guard ring disposed in a second region. The semiconductor device may include a first metal line and a second metal line respectively disposed over the first guard ring and the second guard ring, and respectively coupled to the first guard ring and the second guard ring. The semiconductor device may include a gate pattern coupled to the first metal line or the second metal line, wherein the first metal line and the second metal line are configured to respectively receive a first voltage and a second voltage. The second voltage may have a different potential from the first voltage.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: September 25, 2018
    Assignee: SK hynix Inc.
    Inventor: Wang Su Kim
  • Patent number: 10084058
    Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Mantu K. Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
  • Patent number: 10084032
    Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Li Huang, Chi-Cheng Chen, Hon-Lin Huang, Chien-Chih Chou, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10084118
    Abstract: A semiconductor light-emitting device includes: a package substrate having a mounting surface on which a first circuit pattern and a second circuit pattern are disposed; a semiconductor LED chip mounted on the mounting surface, having a first surface which faces the mounting surface and on which a first electrode and a second electrode are disposed, a second surface opposing the first surface, and side surfaces located between the first surface and the second surface, the first electrode and the second electrode being connected to the first circuit pattern and the second circuit pattern, respectively; a wavelength conversion film disposed on the second surface; and a side surface inclined portion disposed on the side surfaces of the semiconductor LED chip, providing inclined surfaces, and including a light-transmitting resin containing a wavelength conversion material.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mi Jeong Yun, Jong Sup Song