Patents Examined by Mary Wilczewski
  • Patent number: 11121177
    Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11121021
    Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.
    Type: Grant
    Filed: August 12, 2018
    Date of Patent: September 14, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman
  • Patent number: 11121237
    Abstract: The invention discloses a manufacturing method for FinFET device, comprises following steps: S01: providing an SOI substrate; S02: covering a middle part of the top silicon layer by using a barrier layer, and performing a silicon ion implantation on the top silicon layer, so that the buried insulator layer under the top silicon layer not covered by the barrier layer is converted into silicon-rich silicon dioxide, wherein in the top silicon layer, the part not covered by the barrier layer is called an implanted region, and the part covered by the barrier layer is called a non-implanted region; S03: removing the barrier layer, define a fin structure in the top silicon layer, the fin structure includes a channel and a source and drain, the source and drain are located on opposite sides of the channel; and the channel in the fin structure is located in the non-implanted region of the top silicon layer, the source and drain are located in the implanted region of the top silicon layer; removing the top silicon laye
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 14, 2021
    Assignee: SHANGHAI IC R&D CENTER CO., LTD
    Inventor: Lei Song
  • Patent number: 11114299
    Abstract: A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 7, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Kyu-Ha Shim, Rajesh Prasad
  • Patent number: 11107746
    Abstract: A lead frame (4) includes an inner lead (5), an outer lead (2) connected to the inner lead (5), and a power die pad (7). A power semiconductor device (9) is bonded onto the power die pad (7). A first metal thin line (11) electrically connects the inner lead (5) and the power semiconductor device (9). Sealing resin (1) seals the inner lead (5), the power die pad (7), the power semiconductor device (9), and the first metal thin line (11). The sealing resin (1) includes an insulating section (15) directly beneath the power die pad (7). A thickness of the insulating section (15) is 1 to 4 times a maximum particle diameter of inorganic particles in the sealing resin (1). A first hollow (14) is provided on an upper surface of the sealing resin (1) directly above the power die pad (7) in a region without the first metal thin line (11) and the power semiconductor device (9).
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: August 31, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Kawashima, Takamasa Iwai, Taketoshi Shikano, Satoshi Kondo, Ken Sakamoto
  • Patent number: 11107721
    Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a plurality of second transistors atop at least a portion of the first metal layer, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where the plurality of second transistors are vertically oriented transistors, and where the plurality of second transistors are at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the plurality of second transistors, where the second metal layer is aligned to the first metal layer with less than 150 nm misalignment, and where at least one of the second transistors is a junction-less transistor.
    Type: Grant
    Filed: January 10, 2021
    Date of Patent: August 31, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11107740
    Abstract: A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 31, 2021
    Assignee: ABB Power Grids Switzerland AG
    Inventors: Jürgen Schuderer, Umamaheswara Vemulapati, Marco Bellini, Jan Vobecky
  • Patent number: 11094535
    Abstract: Methods for selective deposition, and structures thereof, are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. A passivation layer is selectively formed from vapor phase reactants on the first surface while leaving the second surface without the passivation layer. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the passivation layer. The first surface can be metallic while the second surface is dielectric, or the second surface is dielectric while the second surface is metallic. Accordingly, material, such as a dielectric, can be selectively deposited on either metallic or dielectric surfaces relative to the other type of surface using techniques described herein. Techniques and resultant structures are also disclosed for control of positioning and shape of layer edges relative to boundaries between underlying disparate materials.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: August 17, 2021
    Assignee: ASM IP HOLDING B.V.
    Inventors: Eva E. Tois, Suvi P. Haukka, Raija H. Matero, Elina Färm, Delphine Longrie, Hidemi Suemori, Jan Willem Maes, Marko Tuominen, Shaoren Deng, Ivo Johannes Raaijmakers, Andrea Illiberi
  • Patent number: 11094661
    Abstract: A highly reliable bonded structure having excellent thermal fatigue resistance characteristics and thermal stress relaxation characteristics is provided. The bonded structure of the present invention comprises a first member, a second member capable of being bonded to the first member, and a bonding part interposed between a first bond surface at the first member side and a second bond surface at the second member side to bond the first member and the second member. The bonding part has at least a bonding layer, a reinforcing layer, and an intermediate layer. The bonding layer is composed of an intermetallic compound and bonded to the first bond surface.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: August 17, 2021
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Hirofumi Ito, Masanori Usui, Makoto Kuwahara
  • Patent number: 11088066
    Abstract: An integrated multilayer structure, includes a substrate film having a first side and an opposite second side. The substrate film includes electrically substantially insulating material, a circuit design including a number of electrically conductive areas of electrically conductive material on the first and/or second sides of the substrate film, and a connector including a number of electrically conductive contact elements. The connector is provided to the substrate film so that it extends to both the first and second sides of the substrate film and the number of electrically conductive contact elements connect to one or more of the conductive areas of the circuit design while being further configured to electrically couple to an external connecting element responsive to mating the external connecting element with the connector on the first or second side of or adjacent to the substrate film.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: August 10, 2021
    Assignee: TACTOTEK OY
    Inventors: Jarmo Sääski, Mikko Heikkinen, Tero Heikkinen, Mika Paani, Jan Tillonen, Ronald Haag
  • Patent number: 11088296
    Abstract: A light-emitting diode (LED) substrate and a manufacturing method thereof, and a display device are provided. The LED substrate includes a receiving substrate, the receiving substrate is provided thereon with a pixel definition layer and a plurality of LED units, the pixel definition layer defines a plurality of sub-pixel regions, each of the plurality of sub-pixel regions is configured to receive at least one of the plurality of LED units, and a solder point and an auxiliary metal member are both provided in the sub-pixel region, the auxiliary metal member is provided at a periphery of the solder point, an interval is provided between the solder point and the auxiliary metal member in a plan view of the receiving substrate, and a melting point of the auxiliary metal member is higher than a melting point of the solder point.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: August 10, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Long Wang, Yanzhao Li, Chieh Hsing Chung, Jie Sun
  • Patent number: 11081657
    Abstract: According to one embodiment, a radiation detector includes a first conductive layer, a second conductive layer, and a first layer. The first layer is provided between the first conductive layer and the second conductive layer. The first layer includes a first region and a second region. The first region includes a metal complex including a first metallic element. The second region includes an organic semiconductor material. The first metallic element includes at least one selected from the group consisting of Ir, Pt, Pb, and Cu.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 3, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Wada, Isao Takasu, Rei Hasegawa, Fumihiko Aiga
  • Patent number: 11078075
    Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chih-Ming Chen, Yuan-Chih Hsieh, Chung-Yi Yu
  • Patent number: 11075112
    Abstract: A method includes depositing a first dielectric structure over a non-insulator structure, removing a portion of the first dielectric structure to form a via opening, filling the via opening with a dummy structure, depositing a second dielectric structure over the dummy structure, etching a portion of the second dielectric structure to form a trench over the dummy structure, removing the dummy structure from the via opening, and filling the trench opening and the via opening with a conductive structure, wherein the conductive structure is electrically connected to the non-insulator structure.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 11075201
    Abstract: A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Zhi-Chang Lin, Guan-Lin Chen, Ting-Hung Hsu, Jiun-Jia Huang
  • Patent number: 11075082
    Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Hung Hsieh
  • Patent number: 11069667
    Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 20, 2021
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: David Gani
  • Patent number: 11062959
    Abstract: Embodiments of the invention are directed to a first nanosheet transistor device and a second nanosheet transistor device formed on a substrate. The first nanosheet transistor includes a first inner spacer having a first inner spacer thickness, along with a first gate dielectric having a first gate dielectric thickness. The second nanosheet transistor includes a second inner spacer having a second inner spacer thickness, along with a second gate dielectric having a second gate dielectric thickness. The first inner spacer thickness is greater than the second inner spacer thickness. The first gate dielectric thickness is greater than the second gate dielectric thickness. The first inner spacer thickness combined with the first gate dielectric thickness defines a first combined thickness. The second inner spacer thickness combined with the second gate dielectric thickness defines a second combined thickness. The first combined thickness is substantially equal to the second combined thickness.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 11056382
    Abstract: Structures with a cavity beneath semiconductor devices and methods associated with forming such substrates. A first semiconductor layer is formed on a first side of a first handle wafer. A device structure is formed that is arranged at least in part in the first semiconductor layer. After forming the device structure, the first handle wafer is thinned from a second side of the first handle wafer opposite to the first side of the first handle wafer in order to form a second semiconductor layer from the first handle wafer. After thinning the first handle wafer, a cavity is formed in the second semiconductor layer. The cavity is arranged in the second semiconductor layer beneath the device structure. A second handle wafer is attached to the second semiconductor layer to close the cavity.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, Steven M. Shank
  • Patent number: 11056381
    Abstract: A method for producing a bonded SOI wafer by bonding a bond wafer and a base wafer, each being formed of a silicon single crystal, together with a silicon oxide film placed therebetween, the method including: preparing, as the base wafer, a silicon single crystal wafer whose resistivity is 100 ?·cm or more and initial interstitial oxygen concentration is 10 ppma or less; forming, on the front surface of the base wafer, a silicon oxide film by performing, on the base wafer, heat treatment in an oxidizing atmosphere at a temperature of 700° C. or higher and 1000° C. or lower for 5 hours or more; bonding the base wafer and the bond wafer together with the silicon oxide film placed therebetween; and thinning the bonded bond wafer to form an SOI layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: July 6, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru Ishizuka, Masatake Nakano