Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. A channel-material string is in individual channel openings in the vertically-alternating first tiers and second tiers. A conductor-material contact is in the individual channel openings directly against the channel material of individual of the channel-material strings. The conductor-material contacts are vertically recessed in the individual channel openings. A conductive via is formed in the individual channel openings directly against the vertically-recessed conductor-material contact in that individual channel opening. Other aspects, including structure independent of method, are disclosed.

Abstract: Film information about a thin film formed on the front surface of a semiconductor wafer, substrate information about the semiconductor wafer, and an installation angle of an upper radiation thermometer are set and input. Emissivity of the front surface of the semiconductor wafer formed with a multilayer film is calculated based on the various kinds of information. Further, a weighted average efficiency of the emissivity of the front surface of the semiconductor wafer is determined based on a sensitivity distribution of the upper radiation thermometer. Front surface temperature of the semiconductor wafer at the time of heat treatment is measured using the determined weighted average efficiency of the emissivity. The emissivity is determined based on the film information and the like, so that the front surface temperature of the semiconductor wafer can be accurately measured even when thin films are formed in multiple layers.

Abstract: The present disclosure discloses a semiconductor device and a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes following steps: providing a semiconductor substrate, and forming active regions and trench isolation structures in the semiconductor substrate, wherein the trench isolation structures are located between the active regions; forming first grooves in the active regions; filling the first grooves to form inversion polysilicon layers, the inversion polysilicon layers being inversely doped with the active regions; forming second grooves, the second grooves running through the polysilicon layers and a part of the semiconductor substrate, and reserving parts of the inversion polysilicon layers located on side faces of the second grooves; and, forming buried word line structures in the second grooves.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH3).

Abstract: A substrate processing apparatus includes: a chamber having a container including at least one substrate-heating region and at least one substrate-cooling region; a heating mechanism configured to heat a first substrate in the at least one substrate-heating region; a cooling mechanism configured to cool a second substrate in the at least one substrate-cooling region while the first substrate is being heated; and a partition provided in the container and configured to separate the at least one substrate-heating region and the at least one substrate-cooling region from each other in terms of heat and pressure.

Abstract: A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.

Abstract: A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.

Abstract: An arrangement of linear heat lamps is provided which allows for localized control of temperature nonuniformities in a substrate during semiconductor processing. A reactor includes a substrate holder positioned between a top array and a bottom array of linear heat lamps. At least one lamp of the arrays includes a filament having a varying density and power output along the length of the lamp. In particular, at least one lamp of the arrays includes a filament having a higher filament winding density within a central portion of the lamp relative to peripheral portions of the lamp. In some embodiments, the at least one lamp is a central lamp extending across a central portion of the substrate heated by the lamp. Furthermore, at least one lamp of the arrays has a higher power output within a central portion of the lamp than at peripheral portions of the lamp.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.

Abstract: A three-dimensional (3D) memory device includes a channel structure extending along a first direction and a control gate structure extending along a second direction around the channel structure. Preferably, channel structure includes a negative capacitance (NC) insulating layer, a charge trap structure, and a channel layer, in which the NC insulating layer includes HfZrOx and the charge trap structure includes a blocking layer, a charge trap layer, and a tunneling layer.

Abstract: A stack package includes a core die disposed over a package substrate, and a controller die disposed between the core die and the package substrate to control the core die. The core die includes banks each including memory cell arrays, an interbank region in which row decoders and column decoders are arranged, and a pad region in which first connection pads electrically connected to the row decoders and column decoders through first wirings are disposed. The controller die includes a through via region in which controller die through vias penetrating the controller die to be connected to the first connection pads are disposed, and a circuit region in which controlling circuitry electrically connected to the controller die through vias through second wirings is disposed.

Abstract: A semiconductor storage device includes: a first conductive layer extending in a first direction; a second conductive layer that is disposed apart from the first conductive layer in a second direction intersecting the first direction, and extends in the first direction; a plurality of semiconductor layers provided between the first conductive layer and the second conductive layer and arranged in the first direction, each of which includes a first portion facing the first conductive layer, and a second portion facing the second conductive layer; a plurality of first memory cells provided between the first conductive layer and the semiconductor layers, respectively; and a plurality of second memory cells provided between the second conductive layer and the semiconductor layers, respectively. A gap is provided between the two semiconductor layers adjacent in the first direction.

Abstract: A method includes providing a structure having a substrate, first and second channel layers over the substrate, and first and second gate dielectric layers over the first and the second channel layers respectively. The method further includes forming a first dipole pattern over the first gate dielectric layer, the first dipole pattern having a first dipole material that is of a first conductivity type; forming a second dipole pattern over the second gate dielectric layer, the second dipole pattern having a second dipole material that is of a second conductivity type opposite to the first conductivity type; and annealing the structure such that elements of the first dipole pattern are driven into the first gate dielectric layer and elements of the second dipole pattern are driven into the second gate dielectric layer.

Abstract: A first gate wiring layer is a 2-layered structure in which a polysilicon wiring layer and a metal wiring layer containing aluminum are sequentially stacked. The polysilicon wiring layer and the metal wiring layer surround a periphery of an active region. In a portion of a periphery of the first gate wiring layer, the polysilicon wiring layer and the metal wiring layer contact each other via a contact hole of an interlayer insulating film and in remaining portions thereof, are electrically insulated from each other by the interlayer insulating film. The first gate wiring layer, in portion separate from a gate pad, is configured having relatively more of the metal wiring layer with a resistance value lower than that of the polysilicon wiring layer. The resistance value of the first gate wiring layer is adjusted to be relatively high in a portion near the gate pad, as compared to the portion separate from the gate pad.

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

Abstract: A susceptor for semiconductor substrate processing is disclosed herein. In some embodiments, the susceptor may comprise an inner susceptor portion and an outer susceptor portion. The susceptor portions may self-align via complementary features, such as tabs on the outer susceptor and recesses on the inner susceptor portion. The inner susceptor portion may contain several contact pads with which to support a wafer during semiconductor processing. In some embodiments, the contact pads are hemispherical to reduce contact area with the wafer, thereby reducing risk of backside damage. The inner susceptor portion may contain a cavity with which to receive a thermocouple. In some embodiments, the diameter of the cavity is greater than the diameter of the thermocouple such that the thermocouple does not contact the walls of the cavity during processing, thereby providing highly accurate temperature measurements.

Abstract: A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh is arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction.

Abstract: A method includes forming a fin extending from a substrate; forming an first isolation region along opposing sidewalls of the fin; forming a gate structure over the fin; forming an epitaxial source/drain region in the fin adjacent the gate structure; forming an etch stop layer over the epitaxial source/drain region and over the gate structure; forming a protection layer over the etch stop layer, the protection layer including silicon oxynitride; and forming a second isolation material over the protection layer, wherein forming the second isolation material reduces a nitrogen concentration of the protection layer.

Abstract: The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.

Abstract: A display device includes a substrate, pixels on the substrate, pads, and test lines. The pads are between the pixels and an edge of the substrate and include a first pad and a second pad. The test lines include a first test line and a second test line. The first test line includes a first section and a second section. The second section is closer to the edge of the substrate than the first section and is connected through the first section to the first pad. The second test line includes a first segment and a second segment. The second segment is closer to the edge of the substrate than the first segment and is connected through the first segment to the second pad. A minimum distance between the first section and the first segment is larger than a minimum distance between the second section and the second segment.