Abstract: The semiconductor device includes a first insulating layer; a first oxide semiconductor; a first insulator containing indium, an element M (M is gallium, aluminum, titanium, yttrium, or tin), and zinc; a second oxide semiconductor; a source electrode layer; a drain electrode layer; a second insulator containing indium, the element M, and zinc; a gate insulating layer; and a gate electrode layer. The first and second oxide semiconductors each include a region with c-axis alignment. In the first and second oxide semiconductors, the number of indium atoms divided by sum of numbers of the indium atoms, element M atoms, and zinc atoms is ? or more. In the first insulator, the number of zinc atoms divided by sum of the numbers of indium atoms, element M atoms, and zinc atoms is ? or less.

Abstract: A system having an auxiliary plasma source, disposed proximate the workpiece, for use with an ion beam is disclosed. The auxiliary plasma source is used to create ions and radicals which drift toward the workpiece and may form a film. The ion beam is then used to provide energy so that the ions and radicals can process the workpiece. Further, various applications of the system are also disclosed. For example, the system can be used for various processes including deposition, implantation, etching, pre-treatment and post-treatment. By locating an auxiliary plasma source close to the workpiece, processes that were previously not possible may be performed. Further, two dissimilar processes, such as cleaning and implanting or implanting and passivating can be performed without removing the workpiece from the end station.

Abstract: A method of manufacturing a flip-chip light emitting diode includes: providing a transparent substrate and a temporary substrate, and bonding the transparent substrate with the temporary substrate; grinding and thinning the transparent substrate; providing a light-emitting epitaxial laminated layer having a first surface and a second surface opposite to each other, and including a first semiconductor layer, an active layer and a second semiconductor layer; forming a transparent bonding medium layer over the first surface of the light-emitting epitaxial laminated layer, and bonding the transparent bonding medium layer with the transparent substrate; defining a first electrode region and a second electrode region over the second surface of the light-emitting epitaxial laminated layer, and manufacturing a first electrode and a second electrode; and removing the temporary substrate.

Abstract: Semiconductor devices and fabrication methods are provided. A semiconductor device includes a substrate, a source and drain material layer formed on the substrate. The source and drain material layer contains a first trench there-through. The semiconductor device further includes a mask layer formed on the source and drain material layer containing a second trench there-through. The second trench has a cross-section area larger than the first trench and covers the first trench. The semiconductor device further includes a channel material layer conformally formed on a bottom and sidewalls of each of the first trench and the second trench and a gate structure conformally formed on the channel material layer, on the bottom and the sidewalls of each of the first trench and the second trench. The gate structure has a recess and the recess has a symmetrical step structure.

Abstract: A semiconductor device includes a first external electrode with a first electrode surface portion; a second external electrode with a second electrode surface portion; a MOSFET chip with a built-in Zener diode which includes an active region and a peripheral region; a control IC chip which drives the MOSFET chip based on voltage or current between a drain electrode and a source electrode of the MOSFET chip; and a capacitor which supplies power to the MOSFET chip and the control IC chip. The first electrode surface portion is connected to either the drain electrode or the source, the second electrode surface portion is connected to either the source electrode or the drain electrode, a plurality of unit cells of the MOSFET with the built-in Zener diode are provided in the active region, and the breakdown voltage of the Zener diode is set to be lower than that of the peripheral region.

Abstract: A light emitting device includes a plurality of light emitting elements each including a light extraction surface, a plurality of phosphor layers each covering the light extraction surface of a corresponding one of the light emitting elements with a larger plane area than the light extraction surface, and a plurality of light transmissive members. Each of the light transmissive members has a lower surface facing a corresponding one of the phosphor layers and having a larger plane area than the light extraction surface of a corresponding one of the light emitting elements, an upper surface having a larger plane area than the lower surface, and a side surface having a vertical surface portion contiguous with the upper surface. The light reflecting member surrounds the side surface of each of the light transmissive members.

Abstract: A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

Abstract: The invention describes a method of manufacturing an OLED device (1) comprising an OLED (10) and an integrated negative overvoltage protection diode (11), which method comprises at least the steps of: depositing a first OLED electrode (100) and a separate second OLED electrode contact (101C) on a carrier (12), which second OLED electrode contact (101C) incorporates a first overvoltage protection diode electrode (110); depositing an organic material layer stack (14) to define an active region (14OLED) of the OLED (10) and an active region (14OPD) of the overvoltage protection diode (11); depositing a second OLED electrode (101) to extend over the active region (14OLED) of the OLED (10) and the second OLED electrode contact (101C); and depositing a second overvoltage protection diode electrode (111) to extend over the active region (14OPD) of the overvoltage protection diode (11) and the first OLED electrode (100).

Abstract: Molecular Graphene (MG) of a physical size and bonding character that render the molecule suitable as a channel material in an electronic device, such as a tunnel field effect transistor (TFET). The molecular graphene may be a large polycyclic aromatic hydrocarbon (PAH) employed as a discrete element, or as a repeat unit, within an active or passive electronic device. In some embodiments, a functionalized PAH is disposed over a substrate surface and extending between a plurality of through-substrate vias. Heterogeneous surfaces on the substrate are employed to direct deposition of the functionalized PAH molecule to surface sites interstitial to the array of vias. Vias may be backfilled with conductive material as self-aligned source/drain contacts. Directed self-assembly techniques may be employed to form local interconnect lines coupled to the conductive via material. In some embodiments, graphene-based interconnects comprising a linear array of PAH molecules are formed over a substrate.

Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive.

Abstract: Disclosed is a transistor device. The transistor device includes: in a semiconductor body, a drift region, a body region adjoining the drift region, and a source region separated from the drift region by the body region; a gate electrode dielectrically insulated from the body region by a gate dielectric; a source electrode electrically connected to the source region; at least one field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a rectifier element coupled between the source electrode and the field electrode. The field electrode and the field electrode dielectric are arranged in a first trench that extends from a first surface of the semiconductor body into the semiconductor body. The rectifier element is integrated in the first trench in a rectifier region that is adjacent at least one of the source region and the body region.

Abstract: The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor chip, a semiconductor wafer and a method for manufacturing a semiconductor wafer. The semiconductor chip comprises: a substrate, devices provided on a side of the substrate, via holes running through the substrate, conductive material filled in the via holes and contacted with the devices, and a backside metal layer provided on the other side of the substrate away from the devices, the backside metal layer coming into contact with the conductive material so as to be electrically connected to the devices via the conductive material. The semiconductor chip, the semiconductor wafer and the method for manufacturing a semiconductor wafer of the present disclosure reduce the ground resistance and improve the heat dissipation of devices with via holes structure during the operation.

Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.

Abstract: Disclosed is a method. The method includes forming a trench structure with at least one first trench in a first section of a semiconductor body; forming a second trench that is wider than the first trench in a second section of the semiconductor body; and forming a semiconductor layer on a surface of the semiconductor body in the first section and the second section and in the at least one first trench and the second trench such that the semiconductor layer has a substantially planar surface above the first section and a residual trench remains above the second section. Forming the semiconductor layer includes forming a first epitaxial layer in a first epitaxial growth process and a second epitaxial layer on top of the first epitaxial layer in a second epitaxial growth process.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure and an S/D contact structure formed over the fin structure. The FinFET device structure also includes an S/D conductive plug formed over the S/D contact structure, and the S/D conductive plug includes a first barrier layer and a first conductive layer. The FinFET device structure includes a gate contact structure formed over the gate structure, and the gate contact structure includes a second barrier layer and a second conductive layer. The FinFET device structure includes a first isolation layer surrounding the S/D conductive plug, and the first barrier layer is between the first isolation layer and the first conductive layer. A second isolation layer surrounding the gate contact structure, and the second barrier layer is between the second isolation layer and the second conductive layer.

Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.

Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

Abstract: An optical apparatus includes a cooling device with a lower clad disposed thereon; a waveguide disposed on the lower clad and including an active waveguide to define a gain section and a passive waveguide to define a wavelength-tunable section; gratings disposed in the lower clad of the wavelength-tunable section; an upper clad disposed on the waveguide; a first upper electrode disposed on the upper clad of the gain section; and a second upper electrode disposed on the upper clad of the wavelength-tunable section. The lower clad of the wavelength-tunable section has a recess region to expose an upper surface of the cooling device, the recess region forming an air gap-having a height of 10 ?m to 80 ?m from the upper surface of the cooling device. The gratings are formed in a depth of at least 5 ?m from a bottom surface of the lower clad of the recess region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.