Abstract: A method for transferring electroluminescent structures onto a face, referred to as the accommodating face, of an accommodating substrate. The accommodating face is moreover provided with interconnections intended to individually address each of the structures. The electroluminescent structures are initially formed on a supporting substrate and are separated by tracks. It is then proposed in the present invention to form reflective walls, vertically above the tracks, which comprise a supporting polymer (the second polymer) supporting a metal film on its sides. Such an arrangement of reflective walls makes it possible to reduce the stresses exerted on the electroluminescent structures during the transfer method according to the present invention. Moreover, the reflective walls, within the meaning of the present invention, may be produced on all the electroluminescent structures resting on a supporting substrate.

Abstract: A semiconductor light-emitting element includes: an n-type semiconductor layer; an active layer; a p-side contact electrode made of Rh; a p-side electrode covering layer made of Ti or TiN that covers the p-side contact electrode; a first protective layer made of SiO2 or SiON that covers an upper surface and a side surface of the p-side electrode covering layer in a portion different from that of a first p-side pad opening; a second protective layer made of Al2O3 that covers the first protective layer, a side surface of a p-side semiconductor layer, and a side surface of the active layer in a portion different from that of a second p-side pad opening; and a p-side pad electrode that is in contact with the p-side electrode covering layer in the first p-side pad opening and the second p-side pad opening.

Abstract: A semiconductor body and a method for producing a semiconductor body are disclosed. In an embodiment a semiconductor body includes a p-conducting region, wherein the p-conducting region has at least one barrier zone and a contact zone, wherein the barrier zone has a first magnesium concentration and a first aluminum concentration, wherein the contact zone has a second magnesium concentration and a second aluminum concentration, wherein the first aluminum concentration is greater than the second aluminum concentration, wherein the first magnesium concentration is at least ten times less than the second magnesium concentration, wherein the contact zone forms an outwardly exposed surface of the semiconductor body, and wherein the barrier zone adjoins the contact zone, and wherein the semiconductor body is based on a nitride compound semiconductor material.

Abstract: A light-emitting diode (LED) device includes a light-emitting layer having a core-shell structure that comprises a first semiconductor layer, an active layer, and a second semiconductor layer; a passivation layer formed to cover at least a portion of a side surface and a portion of an upper surface of the second semiconductor layer; a first electrode formed on a portion of the passivation layer that is located on a side surface of the light-emitting layer, the first electrode electrically connected to the first semiconductor layer and including a reflective material; and a second electrode formed on a portion of the passivation layer that is located on an upper surface of the light-emitting layer, the second electrode contacting a portion of the upper surface of the second semiconductor layer that is exposed.

Abstract: A handshake mechanism allows die discovery in a stacked die architecture that keeps inputs isolated until the handshake is complete. Power good indications are used as handshake signals between the die. A die keeps inputs isolated from above until a power good indication from the die above indicates presence of the die above. The die keeps inputs isolated from below until the die detects power is good and receives a power good indication from the die and the die below. In an implementation drivers and receivers, apart from configuration bus drivers and receivers are disabled until a fuse distribution done signal indicates that repairs have been completed. Drivers are then enabled and after a delay to ensure signals are driven, receivers are deisolated. A top die in the die stack never sees a power good indication from a die above and therefore keeps inputs from above isolated. That allows the height of the die stack to be unknown at power on.

Abstract: A light emitting element includes: a semiconductor layered structure; a first electrically insulating film covering surfaces of the semiconductor layered structure and defining a first opening in each of a first region and a second region of a first semiconductor layer, and defining a second opening in a portion above a second semiconductor layer; a first electrode electrically connected to the first semiconductor layer through each first opening; a second electrode electrically connected to the second semiconductor layer through the second opening; a first terminal located on the first electrode and electrically connected to the first electrode; a second terminal located on the second electrode and electrically connected to the second electrode; and a metal member located on a portion of the first electrically insulating film located over the second semiconductor layer and electrically insulated from the first terminal and the second terminal.

Abstract: A display device may include: a substrate; first and second electrode on the substrate; light emitting element between the first and second electrodes; a barrier structure on the substrate and including a first surface, a second surface, and a third surface; a light conversion layer on the barrier structure; and a passivation layer on the light conversion layer. A first space defined by the second and third surfaces may be between the substrate and the barrier structure. A second space defined by the first and second surfaces may be between the barrier structure and the passivation layer. The first and second spaces may be alternately located in the first direction. The light emitting element may be in the first space. The light conversion layer may be in the at least one second space.

Abstract: An electronic device can include a drain terminal, a control terminal, and a source terminal, a first HEMT, and a second HEMT. The first HEMT can include a drain electrode coupled to the drain terminal, a gate electrode coupled to the first control terminal, and a source electrode coupled to the source terminal. The second HEMT can include a drain electrode, a gate electrode, and a source electrode. The drain electrode can be coupled to the drain terminal, and the source electrode can be coupled to the source terminal. In an embodiment, a resistor can be coupled between the gate and source electrodes of the second HEMT, and in another embodiment, the gate electrode of the second HEMT can electrically float. During or after a triggering event, the second HEMT can turn on temporarily to divert some of the charging from the triggering event into the second HEMT.

Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

Abstract: The present technique relates to an electrostatic protective element that enables protective performance with respect to static electricity to be improved and to an electronic device.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: A method includes: introducing a gas including gallium, an ammonia gas, and a gas including a p-type impurity to a reactor and forming a first p-type nitride semiconductor layer on a first light-emitting layer in a state in which the reactor has been heated to a first temperature; lowering a temperature of the reactor from the first temperature to a second temperature; introducing an ammonia gas with a first flow rate to the reactor and increasing the temperature of the reactor from the second temperature to a third temperature; and introducing a gas including gallium, an ammonia gas with a second flow rate, and a gas including an n-type impurity to the reactor, and forming a second n-type nitride semiconductor layer on the first p-type nitride semiconductor layer in a state in which the reactor has been heated to the third temperature.

Abstract: A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.

Abstract: A method for manufacturing a semiconductor device to provide a Metal Insulator Semiconductor Field Effect Transistor (MISFET) in a first region of a semiconductor substrate includes forming a first gate insulating film on the semiconductor substrate in the first region, forming a first gate electrode containing silicon on the first gate insulating film, forming first impurity regions inside the semiconductor substrate so as to sandwich the first gate electrode in the first region, the first impurity regions configuring a part of a first source region and a part of a first drain region, forming a first silicide layer on the first impurity region, forming a first insulating film on the semiconductor substrate so as to cover the first gate electrode and the first silicide layer, polishing the first insulating film so as to expose the first gate electrode, and forming a second silicide layer on the first gate electrode.

Abstract: In a silicon carbide semiconductor device in which a contact electrode is formed on a single-crystal silicon carbide semiconductor substrate, a barrier metal (titanium nitride layer) covers an interlayer insulating film in a region other than a contact hole, and a contact electrode of a predetermined electrode material is formed only in a region on the silicon carbide semiconductor substrate in the contact hole opened in the interlayer insulating film on the silicon carbide semiconductor substrate. A top of the barrier metal is covered by a metal electrode (wiring layer) and no nickel metal aggregates are present between the barrier metal and the metal electrode.

Abstract: Examples of an integrated circuit with a contacting gate structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a memory cell that includes a plurality of fins and a gate extending over a first fin of the plurality of fins and a second fin of the plurality of fins. The gate includes a gate electrode that physically contacts the first fin and a gate dielectric disposed between the gate electrode and the second fin. In some such examples, the first fin includes a source/drain region and a doped region that physically contacts the gate electrode.

Abstract: An optoelectronic component and a method for manufacturing an optoelectronic component are disclosed. In an embodiment an optoelectronic component includes a diffractive optical element comprising at least one conversion material and a light source configured to emit primary radiation, wherein the conversion material is encapsulated in the diffractive optical element, and wherein the conversion material is arranged in a beam path of the primary radiation and is configured to convert the primary radiation at least partially into secondary radiation.

Abstract: A bi-directional optical module includes a substrate, at least one first light-emitting diode (LED), and at least one second LED. The first LED is disposed on a surface of the substrate. The first LED has a first reflection surface and a first light-outlet surface that are opposite to each other, and the first light-outlet surface is away from the substrate relative to the first reflection surface. The second LED is disposed on the same surface of the substrate. The second LED has a second reflection surface and a second light-outlet surface that are opposite to each other, and the second light-outlet surface is close to the substrate relative to the second reflection surface. The substrate has at least one light-transparent area that is not occupied by the first LED and the second LED.

Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.