Abstract: A transparent thin film display element (100) with a display region(101), and a transition region (105) having a first edge (106) bordering the display region and a second edge (107) opposite to the first edge, the transparent display element having a layer stack (103) comprises:a first conductor layer (110); a second conductor layer (120); and an emissive layer (130) superposed between the first and the second conductor layers and configured to emit light upon electrical current flowing through the emissive layer between the first and the second conductor layers. At least one layer (120) of a group comprising the first and the second conductor layers and the emissive layer has, in the transition region (105), a first coverage at the first edge (106), a second coverage lower than the first coverage at the second edge (107), and an intermediate coverage lying between the first and the second coverage.

Abstract: An optical isolation material may be applied to walls of a first cavity and a second cavity in a wafer mesh. A wavelength converting layer may be deposited into the first cavity to create a first segment and into the second cavity to create a second segment. The first segment may be attached to a first light emitting device to create a first pixel and the second segment to a second light emitting device to create a second pixel. The wafer mesh may be removed.

Abstract: Methods and apparatus for forming a bond pad of a semiconductor device such as a backside illuminated (BSI) image sensor device are disclosed. The substrate of a device may have an opening at the backside, through the substrate reaching the first metal layer at the front side of the device. A buffer layer may be formed above the backside of the substrate and covering sidewalls of the substrate opening. A pad metal layer may be formed above the buffer layer and in contact with the first metal layer at the bottom of the substrate opening. A bond pad may be formed in contact with the pad metal layer. The bond pad is connected to the pad metal layer vertically above the substrate, and further connected to the first metal layer of the device at the opening of the substrate.

Abstract: A photodetector includes: a photoelectric conversion layer including a first principal surface from which light enters and a second principal surface on the opposite side from the first principal surface and configured to perform photoelectric conversion on the light; a first diffraction grating formed on a side of the second principal surface and including a configuration where first surfaces which extend in a stripe state in a first direction and second surfaces which extend in a stripe state in the first direction and have a height difference with respect to the first surfaces are alternately arranged; metal wires provided at intervals over the first surfaces and the second surfaces and which extend in the first direction or a second direction perpendicular to the first direction; and a second diffraction grating formed over the first diffraction grating and including grooves which are formed at intervals and extend in the second direction.

Abstract: A semiconductor device and method of forming the same are disclosed. The method of forming a semiconductor device includes providing a substrate, an isolation structure over the substrate, and at least two fins extending from the substrate and through the isolation structure; etching the at least two fins, thereby forming at least two trenches; growing first epitaxial features in the at least two trenches; growing second epitaxial features over the first epitaxial features in a first growth condition; and after the second epitaxial features reach a target critical dimension, growing the second epitaxial features in a second growth condition different from the first growth condition.

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.

Abstract: Described herein are LED chips comprising pluralities of active regions on the same submount. These active regions are individually addressable, such that beam output from the LEDs can be controlled simply by selectively activating the desired active region in the plurality without resorting to incorporation of advanced optics and reflectors comprising complex moving parts. In some embodiments, one or more active regions can surround one or more other active regions. In some embodiments, the various active regions are individually addressable by virtue of each active region comprising its own anode and sharing a common cathode. In some embodiments, the various active regions are individually addressable by virtue of each active region comprising its own cathode and sharing a common anode. In some embodiments, each active region comprises its own anode and its own cathode.

Abstract: A deep ultraviolet light-emitting element of this disclosure includes, in this order, an n-type semiconductor layer; a light-emitting layer; and a p-type semiconductor layer. An emission spectrum of the deep ultraviolet light-emitting element has a primary emission peak wavelength in a wavelength range of 200 nm or more and 350 nm or less, and a blue-violet secondary light emission component having a relative emission intensity of 0.03% to 10% across a wavelength range of 430 to 450 nm, a yellow-green secondary light emission component having a relative emission intensity of 0.03 to 10% across a wavelength range of 540 to 580 nm, when the relative emission intensities are expressed relative to an emission intensity at the primary emission peak wavelength taken as 100%. The ratio of an emission intensity at a wavelength of 435 nm to an emission intensity at a wavelength of 560 nm is 0.5 to 2.

Abstract: A semiconductor device includes a wiring substrate including a first surface, a second surface opposite to the first surface, a first heat dissipation conductive pattern formed on the first surface, a second heat dissipation conductive pattern formed on the first surface, a first wiring formed on the first surface, and a second wiring formed on the first surface. The semiconductor device also includes a semiconductor chip disposed on the wiring substrate and including a third surface and a fourth surface opposite to the third surface. In plan view, the second wiring is adjacent to the first and second heat dissipation conductive patterns without intervening any wiring and any conductive pattern between the second wiring and the first and second heat dissipation conductive patterns.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.

Abstract: Light-emitting diodes (LEDs), LED arrays, and related devices are disclosed. An LED device includes a first LED chip and a second LED chip mounted on a submount with a light-altering material in between. The light-altering material may include at least one of a light-reflective material and/or a light-absorbing material. Individual wavelength conversion elements may be arranged on each of the first and second LED chips. The light-altering material may improve the contrast between the first and second LED chips as well as between the individual wavelength conversion elements. The light-altering material may include at least one of nanoparticles, nanowires, mesowires, or combinations thereof. LED devices may include submounts in modular configurations where LED chips may be mounted on adjacent submounts to form an LED array.

Abstract: A capacitor is provided. The capacitor includes a substrate that has opposing first and second main surfaces. The capacitor also includes at least two conductive plates that are formed in the substrate and extend from the first main surface to the second main surface of the substrate. The capacitor further includes at least one insulating structure that is formed between two adjacent conductive plates of the at least two conductive plates and extends from the first main surface to the second main surface.

Abstract: Aspects of the disclosure provide a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).

Abstract: An image sensor assembly and a method for assembling. The assembly includes: a ceramic package; at least one wall raised from the ceramic package, one of the walls for dividing a first surface region and a second surface region of the ceramic package; a frame supported by the ceramic package; a first set of fiducial markers and a second set of fiducial markers visible on the frame; a first die for placement onto the first surface region, the first die including an image sensor and respective fiducial markers for alignment with the first set of fiducial markers; a second die for placement onto the second surface region, the second die including an image sensor and respective fiducial markers for alignment with the second set of fiducial markers; and at least one optical filter each associated with one of the dice and supported by at least one of the walls.

Abstract: A pixel arrangement structure, a display substrate and a display device. The pixel arrangement structure includes: a plurality of first sub-pixels and a plurality of sub-pixel groups arranged in an array, wherein the plurality of first sub-pixels and the plurality of sub-pixel groups are alternately arranged along a first direction to form pixel rows, and are alternately arranged along a second direction intersected with the first direction to form pixel columns; each of the plurality of sub-pixel groups includes a second sub-pixel, a third sub-pixel and another second sub-pixel sequentially arranged along the first direction; in the same pixel row, a ratio of a distance between the geometric centers of each second sub-pixel and the adjacent third sub-pixel to a distance between the geometric centers of each first sub-pixel and the third sub-pixel in the adjacent sub-pixel group is greater than or equal to ¼ and less than ½.

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

Abstract: A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.

Abstract: A display apparatus is provided. The display apparatus includes a display substrate and a plurality of pads arranged above the display substrate. Each of the plurality of pads includes a first conductive layer, at least a portion of which is covered by an insulating film, a second conductive layer arranged above the first conductive layer, and a clamping portion formed in the second conductive layer.