Abstract: In an embodiment, a method includes: connecting a light emitting diode to a substrate; encapsulating the light emitting diode with a photosensitive encapsulant; forming a first opening through the photosensitive encapsulant adjacent the light emitting diode; and forming a conductive via in the first opening.

Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.

Abstract: A carrier film according to an embodiment of the present invention comprises: a base film; and a first adhesive layer formed on a surface of the base film such that an element to be transferred is attached to the first adhesive layer, wherein the magnitude of force of adhesion between the element and the first adhesive layer is in proportion to the depth of press-fitting at which the element is press-fitted into the first adhesive layer.

Abstract: A display panel and a display device are provided. The display panel includes a substrate, a plurality of signal lines, a plurality of fan-out lines, and a resistance balance member. The substrate defines a display area and a fan-out area. The signal lines are defined in the display area, and the fan-out lines are defined in the fan-out area and are electrically communicated with the signal lines. The fan-out area defines a central winding line region and a peripheral straight line region. The resistance balance member is connected to one fan-out line of the peripheral straight line region in series.

Abstract: Devices and techniques are disclosed herein which include a die including side surfaces such that light emitted from the die can exit through the side surfaces. The die includes a first surface and a second surface opposite the first surface such that the distance between the first surface and the second surface is at least 100 micro meters. The die also include a wavelength converting material deposited external to the die such that the wavelength converting material covers the side surfaces. The wavelength converting material includes phosphor particles, a transparent risen carrier, and transparent particles configured to increase the volume of the wavelength converting material, the transparent particles having a refractive index (RI) that is similar to the RI of the transparent risen carrier.

Abstract: A structure including a first layer of one or more molecular components having a first top anchor group, a first functional moiety and a first bottom anchor group. The first functional moiety connects the first top anchor group to the first bottom anchor group. The structure further includes a first conductive film of one or more nanoparticles disposed on the first layer of one or more molecular components. Each of at least a portion of the one or more nanoparticles bond with the first top anchor group of the one or more molecular components. Each of at least a portion of the one or more nanoparticles cross-link with at least one other of the nanoparticles. The first conductive film forms a first contact for the first layer of one or more molecular components.

Abstract: One of embodiments is a method of manufacturing driven element chips by dividing a semiconductor wafer into the driven element chips. The method includes preparing a semiconductor wafer which includes chip substrate portions arrayed in an array direction, and a clearance between the chip substrate portions adjacent to each other in the array direction. Each chip substrate portion includes: a conductive layer provided inside the chip substrate portion and including interconnect portions; and a dummy conductor provided in a part of the conductive layer where the interconnect portions are not provided.

Abstract: A Static Random-Access Memory (SRAM) device and its manufacturing method are presented, relating to semiconductor techniques. The SRAM device includes: a substrate; a first semiconductor column for Pull-Up (PU) transistors and a second semiconductor column for Pull-Down (PD) transistors, with both the first and the second semiconductor columns on the substrate; a first separation region, and a gate stack structure. The first separation region is between the first and the second semiconductor columns and comprises a first region and a second region, the gate stack structure comprises a gate dielectric layer comprising a first part and a second part; a P-type work function regulation layer comprising a first area and a second area adjacent to each other; a N-type work function regulation layer comprising a third area and a fourth area adjacent to each other; and a gate on both the P-type and N-type work function regulation layers.

Abstract: In a memory device, a lower memory cell string is formed over a substrate to include a first channel structure, a plurality of first word line layers and first insulating layers. The first channel structure protrudes from the substrate and passes through the first word line layers and first insulating layers. An inter deck contact is formed over the lower memory cell string and connected with the first channel structure. An upper memory cell string is formed over the inter deck contact. The upper memory cell string includes a second channel structure, a plurality of second word lines and second insulating layers. The second channel structure passes through the second word lines and second insulating layers, and extends to the inter deck contact, and further extends laterally into the second insulating layers. A channel dielectric region of the second channel structure is above the inter deck contact.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: An organic light emitting diode device comprising: a light emitting layer or layers combining both an emissive material comprising a boron subphthalocyanine, or first emitting layer component, that emits substantially orange light; and an emissive material emitting blue light, or second emitting layer component; wherein in combination, the first emitting layer component and the second emitting layer component, in combination, produces an overall white or near-white light emission.

Abstract: Solid-state light emitting devices including light-emitting diodes (LEDs), and more particularly packaged LEDs that include individually controllable LED chips are disclosed. In some embodiments, an LED package includes electrical connections configured to reduce corrosion of metals within the package; or decrease the overall forward voltage of the LED package; or provide an electrical path for electrostatic discharge (ESD) chips. In some embodiments, an LED package includes an array of LED chips, each of which is individually controllable such that individual LED chips or subgroups of LED chips may be selectively activated or deactivated. A single wavelength conversion element may be provided over the array of LED chips, or separate wavelength conversion elements may be provided over one or more individual LED chips of the array. Representative LED packages may be beneficial for applications where a high luminous intensity with a controllable brightness or adaptable emission pattern is desired.

Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A sandwich gate dielectric layer structure is disposed on the second active layer. A passivation layer is disposed over the sandwich gate dielectric layer structure. A gate extends through the passivation layer to the sandwich gate dielectric layer structure. First and second ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.

Abstract: A semiconductor device includes a first group of trench-like structures and a second group of trench-like structures. Each trench-like structure in the first group includes a gate electrode contacted to gate metal and a source electrode contacted to source metal. Each of the trench-like structures in the second group is disabled. The second group of disabled trench-like structures is interleaved with the first group of trench-like structures.

Abstract: Embodiments of the present invention are directed to techniques for integrating a split gate metal-oxide-nitride-oxide-semiconductor (SG-MONOS) memory with a vertical field effect transistor (VFET). In a non-limiting embodiment of the invention, a vertical SG-MONOS memory device is formed on a first region of a substrate. The SG-MONOS memory device can include a charge storage stack, a memory gate on the charge storage stack, and a control gate vertically stacked over the charge storage stack and the memory gate. A VFET is formed on a second region of the substrate. The VFET can include a logic gate.

Abstract: Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.

Abstract: A pixel arrangement structure is disclosed. The structure includes multiple first pixel rows and multiple second pixel rows arranged alternately. Wherein each of the first pixel rows includes multiple first sub-pixels and multiple second sub-pixels disposed alternately and at intervals, and each of the second pixel rows includes multiple third sub-pixels disposed at intervals. Wherein the first sub-pixel and the second sub-pixel adjacent to the third sub-pixel form a virtual triangle, the third sub-pixel is disposed in the virtual triangle formed by the first sub-pixel and the second sub-pixel adjacent to the third sub-pixel. Applying the pixel arrangement structure to an OLED display panel can improve the resolution, reduce the fabrication difficulty, increase the pixel area, and improve the brightness and life of the OLED display panel.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary semiconductor structure includes a semiconductor substrate having a plurality of cell regions. Each of the cell regions includes a device region, a protection region surrounding the device region and an isolation region surrounding the device region and the protection region. The semiconductor structure also includes a device structure on the semiconductor substrate in the device region; a protection ring structure on the semiconductor substrate in the protection region; an isolation structure on the semiconductor substrate in the isolation region; a passivation layer on the protection ring structure, the device structure and the isolation structure; and a trench passing through the passivation layer in the isolation region.

Abstract: A metal-oxide-semiconductor field-effect transistor includes a wide bandgap substrate, a wide bandgap drift layer over the substrate, a number of junction implants in the drift layer, and a JFET region between the junction implants. The JFET region is defined by a JFET gap, which is the distance between adjacent ones of the junction implants. The JFET gap is not uniform throughout the MOSFET device. The JFET region is separated into a first JFET sub-region and a second JFET sub-region, such that a doping concentration in the first JFET sub-region is different from a doping concentration in the second JFET sub-region.