Abstract: A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Abstract: An electronic module includes a substrate that includes a first main surface and a second main surface, at least one first electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes a hollow portion, at least one second electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes no hollow portion, and a sealing resin. The at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin. The at least one second electronic component is mounted on the second main surface of the substrate and is not sealed with the sealing resin.

Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

Abstract: In a light emitting device, a columnar part includes a first semiconductor layer, a second semiconductor layer different in conductivity type from the first semiconductor layer, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer is disposed between the substrate and the light emitting layer, the light emitting layer includes a first layer, and a second layer larger in bandgap than the first layer, the first semiconductor layer has a facet plane, the first layer has a facet plane, the facet plane of the first semiconductor layer is provided with the first layer, and ?2>?1, in which ?1 is a tilt angle of the facet plane of the first semiconductor layer with respect to a surface of the substrate provided with the laminated structure, and ?2 is a tilt angle of the facet plane of the first layer provided to the facet plane of the first semiconductor layer with respect to the surface of the substrate.

Abstract: This disclosure is directed to systems and methods for maskless gap integration in interconnects having one or more vias above one or more interconnect lines (for example, metal interconnect lines). In various embodiments, the systems and methods described in the disclosure may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines from electrical shorting during subsequent metal layer depositions in a fabrication sequence of the interconnects. Further, in various embodiments, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps, for example, without the need for additional lithography steps.

Abstract: A first component with a first sidewall and a second component with a second sidewall may be mounted onto an expandable film such that an original distance X is the distance between the first sidewall and the second sidewall. The expandable film may be expanded such that an expanded distance Y is the distance between the first sidewall and the second sidewall and expanded distance Y is greater than original distance X. A first sidewall material may be applied within at least a part of a space between the first sidewall and the second sidewall. The expandable film may be expanded such that a contracted distance Z is the distance between the first sidewall and the second sidewall, and contracted distance Z is less than expanded distance Y.

Abstract: A transparent thin film display element (100) with a display region(101), and a transition region (105) having a first edge (106) bordering the display region and a second edge (107) opposite to the first edge, the transparent display element having a layer stack (103) comprises:a first conductor layer (110); a second conductor layer (120); and an emissive layer (130) superposed between the first and the second conductor layers and configured to emit light upon electrical current flowing through the emissive layer between the first and the second conductor layers. At least one layer (120) of a group comprising the first and the second conductor layers and the emissive layer has, in the transition region (105), a first coverage at the first edge (106), a second coverage lower than the first coverage at the second edge (107), and an intermediate coverage lying between the first and the second coverage.

Abstract: An optical isolation material may be applied to walls of a first cavity and a second cavity in a wafer mesh. A wavelength converting layer may be deposited into the first cavity to create a first segment and into the second cavity to create a second segment. The first segment may be attached to a first light emitting device to create a first pixel and the second segment to a second light emitting device to create a second pixel. The wafer mesh may be removed.

Abstract: Methods and apparatus for forming a bond pad of a semiconductor device such as a backside illuminated (BSI) image sensor device are disclosed. The substrate of a device may have an opening at the backside, through the substrate reaching the first metal layer at the front side of the device. A buffer layer may be formed above the backside of the substrate and covering sidewalls of the substrate opening. A pad metal layer may be formed above the buffer layer and in contact with the first metal layer at the bottom of the substrate opening. A bond pad may be formed in contact with the pad metal layer. The bond pad is connected to the pad metal layer vertically above the substrate, and further connected to the first metal layer of the device at the opening of the substrate.

Abstract: A photodetector includes: a photoelectric conversion layer including a first principal surface from which light enters and a second principal surface on the opposite side from the first principal surface and configured to perform photoelectric conversion on the light; a first diffraction grating formed on a side of the second principal surface and including a configuration where first surfaces which extend in a stripe state in a first direction and second surfaces which extend in a stripe state in the first direction and have a height difference with respect to the first surfaces are alternately arranged; metal wires provided at intervals over the first surfaces and the second surfaces and which extend in the first direction or a second direction perpendicular to the first direction; and a second diffraction grating formed over the first diffraction grating and including grooves which are formed at intervals and extend in the second direction.

Abstract: A semiconductor device and method of forming the same are disclosed. The method of forming a semiconductor device includes providing a substrate, an isolation structure over the substrate, and at least two fins extending from the substrate and through the isolation structure; etching the at least two fins, thereby forming at least two trenches; growing first epitaxial features in the at least two trenches; growing second epitaxial features over the first epitaxial features in a first growth condition; and after the second epitaxial features reach a target critical dimension, growing the second epitaxial features in a second growth condition different from the first growth condition.

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.

Abstract: Described herein are LED chips comprising pluralities of active regions on the same submount. These active regions are individually addressable, such that beam output from the LEDs can be controlled simply by selectively activating the desired active region in the plurality without resorting to incorporation of advanced optics and reflectors comprising complex moving parts. In some embodiments, one or more active regions can surround one or more other active regions. In some embodiments, the various active regions are individually addressable by virtue of each active region comprising its own anode and sharing a common cathode. In some embodiments, the various active regions are individually addressable by virtue of each active region comprising its own cathode and sharing a common anode. In some embodiments, each active region comprises its own anode and its own cathode.

Abstract: A deep ultraviolet light-emitting element of this disclosure includes, in this order, an n-type semiconductor layer; a light-emitting layer; and a p-type semiconductor layer. An emission spectrum of the deep ultraviolet light-emitting element has a primary emission peak wavelength in a wavelength range of 200 nm or more and 350 nm or less, and a blue-violet secondary light emission component having a relative emission intensity of 0.03% to 10% across a wavelength range of 430 to 450 nm, a yellow-green secondary light emission component having a relative emission intensity of 0.03 to 10% across a wavelength range of 540 to 580 nm, when the relative emission intensities are expressed relative to an emission intensity at the primary emission peak wavelength taken as 100%. The ratio of an emission intensity at a wavelength of 435 nm to an emission intensity at a wavelength of 560 nm is 0.5 to 2.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.

Abstract: A semiconductor device includes a wiring substrate including a first surface, a second surface opposite to the first surface, a first heat dissipation conductive pattern formed on the first surface, a second heat dissipation conductive pattern formed on the first surface, a first wiring formed on the first surface, and a second wiring formed on the first surface. The semiconductor device also includes a semiconductor chip disposed on the wiring substrate and including a third surface and a fourth surface opposite to the third surface. In plan view, the second wiring is adjacent to the first and second heat dissipation conductive patterns without intervening any wiring and any conductive pattern between the second wiring and the first and second heat dissipation conductive patterns.

Abstract: Light-emitting diodes (LEDs), LED arrays, and related devices are disclosed. An LED device includes a first LED chip and a second LED chip mounted on a submount with a light-altering material in between. The light-altering material may include at least one of a light-reflective material and/or a light-absorbing material. Individual wavelength conversion elements may be arranged on each of the first and second LED chips. The light-altering material may improve the contrast between the first and second LED chips as well as between the individual wavelength conversion elements. The light-altering material may include at least one of nanoparticles, nanowires, mesowires, or combinations thereof. LED devices may include submounts in modular configurations where LED chips may be mounted on adjacent submounts to form an LED array.