Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.

Abstract: The present disclosure relates to an explosion resistant electronic module having a high-speed interface and a method for electronic contacting of such electronic module via such interface. The electronic module includes an electronic component, an electrical contact area for electrical contacting the electronic component and an encapsulation, which encapsulates at least the electrical contact area. The encapsulation is embodied such that the contact area is contactable through the encapsulation by an electrical contact pin, wherein the encapsulation is filled at least in a portion with a self-healing gelatinous potting compound, which enables the encapsulation to be re-sealed after removal of the contact pin.

Abstract: A thin film transistor includes a pair of auxiliary structures facing each other on a substrate, an active layer including an organic semiconductor and continuously grown between the pair of auxiliary structures, a gate electrode on the substrate and overlapped by the active layer, and a source electrode and a drain electrode electrically connected to the active layer. A method of manufacturing the thin film transistor is disclosed.

Abstract: The object is providing an organic light emitting display device achieving a narrow bezel. A display device 10 has a first substrate 11, a second substrate 12, a sealant 25 sealing between the substrates, a display unit 15 including pixel circuits, a driving circuit 20 including a transistor for driving the pixel circuits, a first wiring unit for supplying voltage to the transistor, and a second wiring unit connecting between the transistor and the first wiring unit. The driving circuit 20 is disposed outside the display unit 15, the first wiring unit is disposed between the display unit 15 and the driving circuit 20, the display unit 15 and the first wiring unit are disposed between the first substrate 12 and the second substrate 12, the melting point of a second metal constituting the second wiring unit is higher than that of a first metal constituting the first wiring unit.

Abstract: Back side illumination (BSI) image sensors are provided. A BSI image sensor includes a substrate and a plurality of pixels configured to generate electrical signals responsive to light incident on the substrate. Each of the plurality of pixels includes a photodiode, an infrared radiation (IR) cut-off filter above the photodiode, a light shield pattern above the photodiode and including an opening corresponding to an area of 1 to 15% of each of the plurality of pixels, a planarization layer on the light shield pattern, and a lens on the planarization layer.

Abstract: Back side illumination (BSI) image sensors are provided. A BSI image sensor includes a substrate and a plurality of pixels configured to generate electrical signals responsive to light incident on the substrate. Each of the plurality of pixels includes a photodiode, an infrared radiation (IR) cut-off filter above the photodiode, a light shield pattern above the photodiode and including an opening corresponding to an area of 1 to 15% of each of the plurality of pixels, a planarization layer on the light shield pattern, and a lens on the planarization layer.

Abstract: A semiconductor package includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and electrically connected to the one or more redistribution layers, an encapsulant disposed on the connection structure and covering at least a portion of the semiconductor chip, and a shielding structure covering at least a portion of the encapsulant. The shielding structure includes a conductive pattern layer having a plurality of openings, a first metal layer covering the conductive pattern layer and extending across the plurality of openings, and a second metal layer covering the first metal layer. The second metal layer has a thickness greater than a thickness of the first metal layer.

Abstract: An imaging device includes: a semiconductor substrate; a first photoelectric converter which is disposed in the semiconductor substrate; a second photoelectric converter different from the first photoelectric converter, which is disposed in the semiconductor substrate; a wiring layer disposed on or above the semiconductor substrate; and a capacitor which is disposed in the wiring layer and surrounds the first photoelectric converter in plan view. The capacitor includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode is connected to one of the first photoelectric converter and the second photoelectric converter.

Abstract: A fluxonium qubit includes a superinductor. The superinductor includes a substrate, and a first vertical stack extending in a vertical direction from a surface of the substrate. The first vertical stack includes a first Josephson junction and a second Josephson junction connected in series along the vertical direction. The superinductor includes a second vertical stack extending in a vertical direction from a surface of the substrate. The second vertical stack includes a third Josephson junction. The superinductor includes a superconducting connector connecting the first and second vertical stacks in series such that the first, second, and third Josephson junctions are connected in series. The fluxonium qubit further includes a shunted Josephson junction connected to the superinductor with superconducting wires such that the first, second, and third Josephson junctions of the superinductor that are in series are connected in parallel with the shunted Josephson junction.

Abstract: Gate structures extending continuously above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure are arranged. At least one local interconnect over the non-active region and between two of the gate structures is selectively arranged, to couple at least one of contacts that is arranged above the first active region to at least one of the contacts that is arranged above the second active region.

Abstract: Packaging methods for semiconductor devices are disclosed. A method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.

Abstract: The TFT substrate has a plurality of pixels and a plurality of TFTs (10). The TFT substrate includes a first conductive layer (12) including a gate electrode (12g) of the TFT, a gate insulating layer (13), a semiconductor layer (14), a protective insulating layer (15) including a portion covering a channel region (14c) and having a first opening portion (15a) reaching the drain electrode (14s) and a second opening portion (15b) reaching the drain region (14d), and a second conductive layer (16) including a source electrode (16s) and a drain electrode (16d). Each of the plurality of pixels has a compensation capacitance unit (30), the first conductive layer further includes a first electrode unit (12a) electrically connected to the gate electrode and forming a compensation capacitance unit, and the second conductive layer further includes a second electrode unit (16a) electrically connected to the drain electrode, overlapping the first electrode unit, and forming a compensation capacitance unit.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a source pad, a drain pad, and a source external connecting element. The source electrode, the drain electrode, and the gate electrode are disposed on an active region of the active layer. The source pad is electrically connected to the source electrode and includes a body portion, a plurality of branch portions, and a current diffusion portion. The body portion is at least partially disposed on the active region of the active layer. The current diffusion portion interconnects the body portion and the branch portions. A width of the current diffusion portion is greater than a width of the branch portion and less than a half of a width of the body portion. The source external connecting element is disposed on the body portion and spaced from the current diffusion portion.

Abstract: The present disclosure provides a semiconductor chip. The semiconductor chip includes a substrate, a main device, a one-time-programmable (OTP) device and a decoupling capacitor array. The substrate includes a first region and a second region. The main device is in the first region, the OTP device and the decoupling capacitor array are in the second region, and the decoupling capacitor array overlies the OTP device.

Abstract: [Object] To make it possible to improve light extraction efficiency while realizing a desired viewing angle characteristic for each pixel. [Solution] Provided is a display device, including: a plurality of light emitting sections formed on a substrate; and reflectors provided above the light emitting sections with respect to the plurality of light emitting sections positioned in at least a partial region of a display surface, lower surfaces of the reflectors reflecting part of emission light from the light emitting sections. The light emitting sections and the reflectors are arranged in a state in which centers of the reflectors are shifted from centers of luminescence surfaces of the light emitting sections in a plane perpendicular to a stacking direction so that light emitted in a direction other than a desired direction among the emission light from the light emitting sections is reflected.

Abstract: A power module of double-faced cooling includes: an upper substrate; a lower substrate on which a plurality of semiconductor chips are disposed; and a first spacer disposed between the upper substrate and the lower substrate, electrically connecting the upper substrate and the lower substrate to each other, and disposed on the lower substrate to be equally distanced from each of the semiconductor chips. Power is supplied to the semiconductor chips on the lower substrate through the upper substrate and the first spacer.

Abstract: In one embodiment, a device is described. The device includes a material defining a reaction region. The device also includes a plurality of chemically-sensitive field effect transistors have a common floating gate in communication with the reaction region. The device also includes a circuit to obtain respective output signals from the chemically-sensitive field effect transistors indicating an analyte within the reaction region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of one-time-programmable (OTP) cells, a bottom cell plate, a top cell plate and a decoupling capacitor array. The substrate includes a plurality of active areas and at least one isolation structure provided between the active areas to isolate the active areas from one another. The plurality of OTP cells are disposed in the active areas, the bottom cell plate is disposed on the OTP cells, and the top cell plate is disposed over the bottom cell plate. The decoupling capacitor array is disposed between the bottom cell plate and the top cell plate, and overlies the OTP cells.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: A pixel array substrate has a plurality of sub-pixel regions, wherein a pixel structure of an individual sub-pixel region includes a first signal line, a second signal line, a first contact pad, a second contact pad, a light-emitting diode, a first conductive structure, and a flux structure layer. The first contact pad and the second contact pad are respectively electrically connected with the first signal line and the second signal line. The light-emitting diode is disposed on the first contact pad. A portion of the first conductive structure is disposed between the first contact pad and a first electrode of the light-emitting diode. The flux structure layer partially surrounds the first conductive structure and the light-emitting diode. A top portion of the flux structure layer is higher than a top surface of the first electrode and is lower than a bottom surface of a light-emitting layer of the light-emitting diode.