Abstract: The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.

Abstract: A display panel, a method for manufacturing the same, a display device and a method for manufacturing the same are provided. The display panel includes a display region and a peripheral region arranged on a substrate, and further includes multiple active driving circuits and multiple redundant driving circuits. At least one active driving circuit is electrically connected to at least one of multiple pixel units, and each redundant driving circuit includes at least one electrode layer arranged on the substrate. The peripheral region includes a flat region and a curved region, at least part of the redundant driving circuits are located in a flat redundant driving circuit region included in the flat region. The flat redundant driving circuit region includes at least two alignment mark regions. In the alignment mark regions, at least one electrode layer is hollowed out, and/or at least one electrode layer is filled up.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines, and a plurality of slit structures. Each memory cell includes a vertical transistor, and a storage unit coupled to the vertical transistor. The array of memory cells is arranged in rows in a first direction and columns in a second direction. Two adjacent rows of the memory cells are staggered with one another, and two adjacent columns of the memory cells are staggered with one another in a plan view. Each word line extends in the second direction. Each slit structure extends in the second direction and separating two adjacent word lines of the plurality of word lines in the first direction.

Abstract: A semiconductor device includes an insulating substrate, semiconductor elements mounted on the insulating substrate, and a cooler for cooling the semiconductor elements. The cooler includes a heat dissipating substrate having bonding and heat dissipating surfaces opposite to each other, the bonding surface being bonded to the second surface of the insulating substrate, a plurality of fins on the heat dissipating surface, a reinforcing plate having first and second surfaces opposite to each other and covering the fins, the first surface being bonded to tips of the fins, and a cooling case including a recessed part to house the fins and reinforcing plate. A first gap between two adjacent fins, measured in a direction parallel to the heat dissipating substrate, is larger than a second gap between the reinforcing plate and a bottom of the first recessed part, measured in a thickness direction.

Abstract: A cover panel includes: a light blocking layer; a cushion layer overlapping with the light blocking layer; a wire overlapping with the cushion layer; and a via hole connected to the wire, and penetrating the light blocking layer and the cushion layer.

Abstract: A display substrate having a plurality of subpixels is provided. A respective one of the plurality of subpixels includes a light emitting element; a first thin film transistor configured to driving light emission of the light emitting element; and a light emitting brightness value detector. The light emitting brightness value detector includes a second thin film transistor; and a photosensor electrically connected to the second thin film transistor and configured to detect a light emitting brightness value. The display substrate further includes a silicon organic glass layer on a side of at least one of the first thin film transistor or the second thin film transistor away from a base substrate; and the photosensor is on a side of the silicon organic glass layer away from the base substrate.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: A semiconductor device includes an active layer having first and second active regions, first and second source electrodes, first and second drain electrodes, first and second gate electrodes, a first source metal layer, first and second drain metal layers, and a source pad electrically connected to the first source metal layer. The second drain metal layer is electrically connected to the second drain electrode and the first source metal layer. A projection of the second drain metal layer on the active layer forms a drain metal layer region. An projection of the source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

Abstract: Methods and apparatus relating to FET arrays including large FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.

Abstract: A display device includes: a substrate on which circuit elements constituting a pixel are arranged; a repair pattern arranged overlying the substrate; a buffer layer covering the repair pattern; an active layer arranged overlying the buffer layer; a conductive layer which is arranged overlying the active layer and on which electrodes of the circuit elements are arranged; an overcoat layer covering the conductive layer; and a light emitting element arranged overlying the overcoat layer. The repair pattern is arranged in such a manner that one region thereof overlaps the active layer.

Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

Abstract: An organic light emitting display device includes a first transistor including a first active region and a first gate electrode disposed on the first active region, a third transistor including a third lower gate electrode disposed on the first gate electrode, a third active region disposed on the third lower gate electrode, and a third upper gate electrode disposed on the third active region, and a fourth transistor including a fourth active region disposed in the same layer as the first active region and a fourth gate electrode disposed on the fourth active region. The first transistor is a first-type transistor, and the fourth transistor is a second-type transistor different from the first-type transistor.

Abstract: A method may be used for manufacturing a semiconductor element. The method may include the following steps: preparing a substrate; forming a semiconductor layer on the substrate, wherein the semiconductor layer includes crystallized two-dimensional layers; forming a source electrode and a drain electrode on the semiconductor layer; forming an semiconductor member by wet etching the semiconductor layer using sodium hypochlorite as an etchant, wherein the wet etching results in a residue; and removing the residue using purified water and an inert gas.

Abstract: A display device includes a base layer including an active area and a peripheral area outside the active area, a circuit element layer including a pixel circuit in the active area and a driving voltage wiring located in the peripheral area to supply a driving voltage to the pixel circuit. A light emitting element layer including a plurality of light emitting elements on the circuit element layer, a thin film sealing layer to cover the light emitting element layer, and an input sensing layer on the thin film sealing layer and including a sensing electrode and a sensing signal wiring part connected to the sensing electrode. The circuit element layer includes a connection wiring part overlapping the driving voltage wiring in the peripheral area and contacts the sensing signal wiring part. The connection wiring part is at a different layer from the driving voltage wiring.

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes: a display substrate, an IC chip, and a circuit board. The display substrate includes a first bonding portion including a first detection pin and a second detection pin, a second bonding portion connected to the first bonding portion and including a first connection pin and second connection pin which are connected by a connection wire included by the circuit board, a first connection line connecting the first detection pin to the first connection pin and including a first crack detection line, and a second connection line connecting the first detection pin to the second connection pin. The IC chip is bonded to the first bonding portion and configured to determine cracks on an edge of the display substrate according to electric signals of the first detection pin and the second detection pin.

Abstract: A display panel, a manufacturing method thereof, and a display device are disclosed. For the display panel, an anti-crack structure is disposed in a chamfer between a driving circuit layer and a substrate. The anti-crack structure is in contact with a packaging layer to reduce an angle from the contact plane of the anti-crack structure and the packaging layer to the plane in which a light-emitting layer is located, so that the packaging layer is smoothly disposed, the risk of the fracture of the packaging layer is lowered, and the failure of the display panel is avoided.