Patents Examined by Matthew E. Gordon
  • Patent number: 11652198
    Abstract: A light-emitting device including a light-emitting module, a first wiring and a second wiring. The light-emitting module includes one or more light-emitting elements and a package covering the one or more light-emitting elements. Each of the one or more light-emitting elements has a first electrode and a second electrode. The light-emitting module has a groove structure on a lower surface side. The first wiring and the second wiring are partially or entirely present in the groove structure. At least part of the first electrode and at least part of the second electrode are exposed to an inside of the groove structure. The first wiring is electrically connected with the first electrode, and the second wiring is electrically connected with the second electrode.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: May 16, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Rie Maeda, Masaaki Katsumata
  • Patent number: 11646274
    Abstract: An integrated circuit package may be formed comprising a substrate that includes a mold material layer and a signal routing layer, wherein the mold material layer comprises at least one bridge and at least one foam structure embedded in a mold material. In one embodiment, the substrate may include the mold material of the mold material layer filling at least a portion of cells within the foam structure. In a further embodiment, at least two integrated circuit devices may be attached to the substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventors: Mufei Yu, Gang Duan, Edvin Cetegen, Baris Bicen, Rahul Manepalli
  • Patent number: 11641768
    Abstract: A display device includes a display panel including a first pad on a base substrate, an adhesive pattern which faces the base substrate with the first pad therebetween, a circuit board electrically connected to the display panel at the first pad and including a second pad facing the first pad, and a plurality of conductive members between the first pad and the second pad to electrically connect the first pad and the second pad to each other. The first pad of the display panel has a planar shape, and each of the plurality of conductive members is within the planar shape of the first pad and penetrates the adhesive pattern to contact the first pad.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: May 2, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: JeongJin Park, Atsushi Nemoto, Young-Min Park, Taeho Lee
  • Patent number: 11637167
    Abstract: A method of manufacturing a display panel includes forming a circuit layer including a gate, a source, and a drain on a base substrate and forming a light emitting element layer on the circuit layer. The forming of the circuit layer includes sequentially forming a preliminary metal layer, a preliminary oxide layer comprising molybdenum and tantalum, and a preliminary capping layer which comprise a preliminary electrode layer, cleaning the preliminary electrode layer, forming a photoresist layer pattern on the preliminary electrode layer, etching the preliminary electrode layer, and removing the photoresist layer pattern. During the etching of the preliminary electrode layer, a ratio between a removal speed ER1 of the preliminary oxide layer and a removal speed ER2 of the preliminary metal layer satisfies Equation 1 to maintain a low reflection property 1?ER2/ER1?3.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 25, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gyungmin Baek, Juhyun Lee, Hongsick Park, Hyuneok Shin
  • Patent number: 11637163
    Abstract: Provided are an array substrate and a manufacturing method of an array substrate and a display panel and device. The array substrate includes a pixel circuit. The pixel circuit includes a first transistor and a second transistor, the first transistor includes a first active layer, the second transistor includes a second active layer, and the first active layer and the second active layer both include silicon. The array substrate further includes a first-type inorganic layer and a second-type inorganic layer and a first via hole. The first via hole is located above the first active layer and at least penetrates through the second-type inorganic layer. Concentration of hydrogen ions in the first active layer is less than concentration of hydrogen ions in the second active layer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: April 25, 2023
    Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
    Inventor: Yong Yuan
  • Patent number: 11637073
    Abstract: A semiconductor device with EMI shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes EMI shield on all six surfaces of the semiconductor device without the use of a discrete EMI lid.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: April 25, 2023
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Doo Soub Shin, Tae Yong Lee, Kyoung Yeon Lee, Sung Gyu Kim
  • Patent number: 11626395
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Pooya Tadayon, Weihua Tang, Chandra M. Jha, Zhimin Wan
  • Patent number: 11626471
    Abstract: A display device includes: a first active pattern on a light blocking pattern; a second active pattern at a same layer as that of the first active pattern; a first insulating pattern on the first active pattern; a second insulating pattern on the first active pattern, the second insulating pattern being spaced from the first insulating pattern, and having a first contact hole exposing the first active pattern; a first gate electrode on the first insulating pattern; a second gate electrode at a same layer as that of the first gate electrode, and overlapping with the second active pattern; a first etch stopper on the second insulating pattern, and having a second contact hole connected to the first contact hole; and a first electrode on the first etch stopper, the first electrode contacting the light blocking pattern and the first active pattern through the first and second contact holes.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: April 11, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youngseok Baek, Sangjin Park, Chongsup Chang, Eui Kang Heo
  • Patent number: 11626575
    Abstract: A display device according to an embodiment may include a base layer including a first surface and a second surface, a pixel circuit layer including a first line on the first surface, a display element layer on the pixel circuit layer and including a display element, a thin film encapsulation layer on the display element layer, a first protective layer on the thin film encapsulation layer, and a second line on the second surface to correspond to the first line. The first protective layer may include a transparent insulating material.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: April 11, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gyung Min Baek, Hyun Ah Sung, Hyun Eok Shin
  • Patent number: 11626469
    Abstract: A display device and a method of fabricating a display device are provided. A display device includes a substrate. The wiring layer includes a conductive metal layer and a metal compound layer of the conductive metal layer, The metal compound layer surrounds the conductive metal layer.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: April 11, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gyung Min Baek, Hyun Eok Shin, Ju Hyun Lee
  • Patent number: 11626477
    Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: April 11, 2023
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
  • Patent number: 11621408
    Abstract: A manufacturing method of a display device includes providing a first organic layer in a display area and a non-display area, to cover a pixel electrode and a pad electrode, respectively, providing a first electrode of a light emitting element, in the display area, the first organic layer being between the pixel electrode and the first electrode, after forming the first electrode, removing a portion of the first organic layer which is in the non-display area, to expose the pad electrode from the first organic layer; and providing a light emitting layer of the light emitting element, corresponding to the first electrode.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 4, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jiyoun Lee, Hyunyoung Kim, Rohyeon Park, Jong-Ryuk Park, Changwook Kang
  • Patent number: 11616050
    Abstract: A method for manufacturing a micro light emitting diode device is provided. A plurality of first type epitaxial structures are formed on a first substrate and the first type epitaxial structures are separated from each other. A first connection layer and a first adhesive layer are configured between the first type epitaxial structures and the first substrate. The first connection layer is connected to the first type epitaxial structures. The first adhesive layer is located between the first connection layer and the first type epitaxial substrate. The Young's modulus of the first connection layer is larger than the Young's modulus of the first adhesive layer. The first connection layer located between any two adjacent first type epitaxial structures is removed so as to form a plurality of first connection portions separated from each other. Each of the first connection portions is connected to the corresponding first type epitaxial structure.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: March 28, 2023
    Assignee: PlayNitride Inc.
    Inventors: Yu-Yun Lo, Tzu-Yang Lin, Yu-Hung Lai
  • Patent number: 11610961
    Abstract: A display device includes a transistor disposed on a substrate and including a gate electrode, a channel region, a source region, and a drain region; a first insulating layer disposed on the transistor; a drain electrode that electrically contacts the drain region through an opening formed in the first insulating layer; a connection electrode disposed on the drain electrode and electrically contacting the drain electrode; a second insulating layer disposed on the first insulating layer, an upper surface of the second insulating layer and an upper surface of the connection electrode forming a flat surface that is parallel to the substrate; a pixel electrode disposed on the flat surface and electrically contacting an upper surface of the connection electrode; an emission layer disposed on the pixel electrode; and a common electrode disposed on the emission layer.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 21, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hyeon Bum Lee
  • Patent number: 11600797
    Abstract: An organic light-emitting display apparatus including a substrate having a display area and a peripheral area; a TFT in the display area; an organic insulating layer on the TFT; an OLED that includes a pixel electrode electrically connected to the TFT, an emission layer on the pixel electrode, and a counter electrode facing the pixel electrode with the emission layer therebetween; a pixel-defining layer on the organic insulating layer and having an opening overlying the pixel electrode; a first dam in the peripheral area; a second dam in the peripheral area to surround an outer periphery of the first dam; a metal-containing layer covering the first dam and including a same material as the pixel electrode; and a thin-film encapsulator on the substrate to cover the OLED and including a first and second inorganic films, and an organic film between the first and second inorganic films.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Kwangchul Jung
  • Patent number: 11600691
    Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Muralikrishnan Balakrishnan, Beth R. Cook, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11600683
    Abstract: Discussed is a display apparatus capable of realizing a high resolution and a small power consumption, and a method for manufacturing the same, wherein the display apparatus includes a bottom gate type first thin film transistor disposed in a display area, and a top gate type second thin film transistor disposed in a non-display area.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: March 7, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Yewon Hong
  • Patent number: 11600557
    Abstract: A packaged semiconductor device includes a lead frame including plurality of lead terminals each having a plated wettable flank dimple including 2 or more different widths including narrower lead terminals and wider lead terminals. A semiconductor die is attached to the lead frame. A mold material terminates at a saw line of the packaged semiconductor device providing encapsulation except for an exposed bottom contact and an exposed sidewall contact for the plurality of lead terminals. The wider lead terminals have a necked region with a reduced width extending inward a predetermined distance from the saw line, where a terminal region inward beyond the necked region which is wider as compared to the necked region.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: March 7, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Robert F. Mortan
  • Patent number: 11594642
    Abstract: In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is inhibited and reliability is improved. The transistor includes a first gate electrode; a first insulating film over the first gate electrode; an oxide semiconductor film over the first insulating film; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode; and a second gate electrode over the second insulating film. The second insulating film includes oxygen. The second gate electrode includes the same metal element as at least one of metal elements of the oxide semiconductor film and has a region thinner than the oxide semiconductor film.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: February 28, 2023
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Daisuke Kurosaki
  • Patent number: 11587993
    Abstract: A display panel and a manufacturing method thereof are provided in the present application. The display panel includes a substrate, a planarization layer disposed on the substrate, and a pixel definition layer disposed on the planarization layer. The display panel includes a test region, wherein a plurality of virtual pixel openings are disposed in the pixel definition layer positioned in the test region, and a plurality of barrier holes in a one-to-one correspondence to the virtual pixel openings are disposed in the planarization layer positioned in the test region, and a barrier layer fills each of the barrier holes.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 21, 2023
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Jinxing Chu, Jinchuan Li