Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.

Abstract: A mobile computer system such as mobile PC operable between a normal, stationary mode and a Navigation mode for optimal system performance and power management for mobile applications.

Abstract: A variable latency cache memory is disclosed. The cache memory includes a plurality of storage elements for storing stack memory data in a first-in-first-out manner. The cache memory distinguishes between pop and load instruction requests and provides pop data faster than load data by speculating that pop data will be in the top cache line of the cache. The cache memory also speculates that stack data requested by load instructions will be in the top one or more cache lines of the cache memory. Consequently, if the source virtual address of a load instruction hits in the top of the cache memory, the data is speculatively provided faster than the case where the data is in a lower cache line or where a full physical address compare is required or where the data must be provided from a non-stack cache memory in the microprocessor, but slower than pop data.

Abstract: Systems and methods which provide an extensible caching framework are disclosed. These systems and methods may provide a caching framework which can evaluate individual parameters of a request for a particular piece of content. Modules capable of evaluating individual parameters of an incoming request may be added and removed from this framework. When a request for content is received parameters of the request can be evaluated by the framework and a cache searched for responsive content based upon this evaluation. If responsive content is not found in the cache, responsive content can be generated and stored in the cache along with associated metadata and a signature formed by the caching framework. This signature may aid in locating this content when a request for similar content is next received.

Abstract: Provided are a method, system, and program for forming a consistency group of data. A command is received to form a consistency group with respect to data received at a first storage site that is mirrored to a second storage site. A first data structure is provided indicating updates to the first storage site not included in the consistency group that are received after the command and a second data structure is provided indicating updates to the first storage site in the consistency group to be formed. A command is transmitted to cause data copied to the second storage site that is part of the consistency group to be copied to a third storage site. Indication is received when the data in the second storage site that is part of the consistency group is copied to the third storage site.

Abstract: A system includes a processor, a storage system having one or more physical storage devices, and a controller coupled to the processor and the storage system. The controller maintains a virtual physical drive (VPD) map that defines a set of virtual physical drives, and maps the virtual physical drives to storage media of the physical storage devices. The controller receives access requests from the processor and controls the physical storage media according to the VPD map such that the virtual physical drives appear to the processor as physically independent drives. The controller provides hardware-level security to prevent unauthorized access by the processor or any software application executing on processor. In addition, the controller may maintain primary virtual storage and secondary virtual storage within the virtual physical drives, and may dynamically reallocate the virtual storage to backup and restore data in a manner that appears almost instantaneous to the user.

Abstract: A method, an apparatus, and a computer program are provided for managing commands in a multi-queue system. Depending on the types of queues that are utilizes, there can be difficulties in managing the order of execution of commands. To alleviate this problem, dependencies and identifiers are associated with each command that allow command queues in the entire multi-queue system to monitor the status of all commands.

Abstract: Where a leakage magnetic field deletes data on adjacent tracks gradually, such deletion is compensated so as to prevent data errors from occurring. A magnetic disk device includes one or more magnetic disks, one or more magnetic heads, and a write and read circuit for writing or reading data, and writes or reads the data on tracks on the magnetic disks. The number of writes of the data on a given track is acquired. If the number of writes reaches a predetermined number, the data on the tracks adjacent to a given track is read out once and, then, the data is rewritten on the adjacent tracks. Further, when the data is written on the tracks, the data is written on alternate physical tracks and every other track is skipped, and after the data is written on half of all tracks, the data is written on the skipped tracks.

Abstract: The bus controller of a bus system supports isochronous messages and non-isochronous messages for which the bus system does and does not support a guaranteed transceiving capacity per time-frame respectively. The system has a first and second memory section for exchange of data from the isochronous messages between a processor and the bus controller. The bus controller has access priority over the processor in alternating first and second ones of the time frames. The bus controller transfers data from isochronous messages between the bus medium and the first and second memory section in the first and second ones of the time frames respectively. The processor has access priority to the first and second memory section over the bus controller in the second and first ones of the time frames respectively.

Abstract: A method to control access to logical volumes disposed in an information storage and retrieval system using parallel access volumes. The method provides an information storage and retrieval system comprising a plurality of logical volumes, and a plurality of host computers, where each host computers is capable of communicating with the information storage and retrieval system. The method creates a parallel access volume having an alias, and persistently associates that parallel access volume with an original base logical volume, where the original base logical volume may be assigned to one of (N) logical volume groups. If the original base logical volume is assigned to the (i)th logical volume group, the method permits each host computers assigned to the (i)th host computer group to access the original base logical volume, or the current base logical volume, associated with the parallel access volume.

Abstract: A data storage control unit is coupled to one or more host devices and to one or more physical storage units, the physical storage units collectives configured as a plurality of logical storage ranks. The storage control unit receives and processes write requests from the host devices and directs that data updates be stored in a temporary storage. The data updates are subsequently destaged to the logical ranks. Write requests are processed at a predetermined rate relative to the rate at which destages are performed (destage mode or rate). The storage control unit evaluates workload conditions of the temporary storage and modifies the destage mode if the temporary storage is in danger of becoming backlogged or if an actual backlog is created, thereby applying a “throttle” to the host write requests. Thus, method, apparatus and program product are provided to dynamically modify a level of throttling whereby through-put of a host device is substantially maintained.

Abstract: A system including a multi-port storage device (e.g., a disk drive) and at least two users, each user coupled to a port of the storage device by a serial link. The storage device has an operational portion and an interface (including arbitration circuitry) between its ports and the operational portion. In response to a set of competing priority bids from the users, the arbitration circuitry grants one bid (including by sending an acknowledgement to the successful bidder) and preferably holds each non-granted competing bid without sending any notification to the unsuccessful bidder until the successful bidder sends a deselect signal. The system can be a RAID system including at least two disk drives and at least two controllers, where at least one drive is a multi-port device shared by at least two of the controllers. Preferably, each priority bid and deselect signal is a primitive code (e.g., an ordered sequence of a 10-bit control character and three 10-bit data characters in SATA format).

Abstract: Systems and methods that cache are provided. In one example, a system may include a spatial cache system coupled to a processing unit and to a memory. The spatial cache system may be adapted to reduce the memory latency of the processing unit. The spatial cache system may be adapted to store prefetched blocks, each stored prefetched block including a plurality of cache lines. If a cache line requested by the processing unit resides in one of the stored prefetched blocks and does not reside in the processing unit, then the spatial cache system may be adapted to provide the processing unit with the requested cache line.

Abstract: A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.

Abstract: The concept of isolated ordered regions to maintain coordinates of nodes is used by associating each node with coordinates relative to a containing region. Modifications to nodes within a region only affect the nodes in that region, and not nodes in other regions. Traversals that retrieve information from the nodes can rebase the coordinates from their containing region and return with a total order. Access patterns and usage are used to recognize and prefetch pages. The probability of revisiting traversed nodes are identified and pages in a bufferpool are replaced based upon the identified probabilities (e.g., replacing pages with the least probability of a revisit).

Abstract: A method and apparatus for balancing memory access latency and bandwidth is generally described. In accordance with one example embodiment of the invention, a method comprising determining at least one characteristic of a memory request, and selectively leaving an accessed memory page open after a memory access based, at least in part, on the at least one characteristic for the memory request, to balance memory access latency and bandwidth of a subsequent memory request(s).

Abstract: A storage system maintains a journal of journal entries and at lease one snapshot of one or more data volumes. By assigning a unique sequence number to journal and snapshot, it is easy to find a journal which can be applied to the snapshot. A technique is described for detecting an overflow condition of running out of journal space and recovering the journal space.

Abstract: An apparatus and method of flash ROM management. The apparatus comprises a storage device, a strapping component and a process unit. The storage device stores multiple address records comprising an identity and an address range associated with a flash ROM. The strapping component is configured to output a signal to determine flash ROM type. The process unit receives a memory access request with an access range from the CPU and the signal from the strapping component queries the identity by matching the access range and the address range, and finally executes an LPC 1.1 memory access instruction with the identity and the access range corresponding to the memory cycle.

Abstract: A Simple Device for creating exact copies of computer long-term memory devices such as hard drives and compact flash memory. Our current invention is a stand-alone device. A user connects a long-term memory device he desires to make a copy of (source) to our device. The user also connects a long-term memory device to receive this copy (destination). Our device contains logic and circuitry, which perform operations on both the source and destination device to make an exact copy of the Source Data to the Destination Device, while protecting the Source device from any changes. Our device has a very simple user interface. This simplified user interface makes it difficult and unlikely to use our device incorrectly.

Abstract: A method and apparatus to perform memory management are described.