Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.

Abstract: The source storage 1220 and source path 1230 constituting backup source information of all of the backup data in a computer system 1000, the destination storage 1240 and destination path 1250 constituting backup destination information and information regarding the backup time-point 1260 are held on an administration console 1010; a backup manager 1020 that runs on the administration console 1010 designates backup between the NAS's and gives instructions for restoration from the backed-up data by using these items of information.

Abstract: For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.

Abstract: A technique efficiently accesses locks associated with resources in a computer system. A processor accesses (e.g., acquires or releases) a lock by specifying and issuing a request to a resource controller, the request containing attribute and resource location information associated with the lock. In response, the resource controller applies the information contained in the request to an outstanding lock data structure to determine if the request should be blocked, blocked as a pending writer, allowed or an error condition. If the request is blocked, it remains blocked until the outstanding lock blocking the request is released. If the request is allowed, operations associated with the request are performed.

Abstract: A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

Abstract: A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in response to N?1 number of the align control signals for receiving N-bit data and outputting the N-bit data in a parallel fashion; and a outputting block in response to the remaining align control signal for receiving the N-bit data in the parallel fashion and synchronizing the N-bit data with the remaining align control signal having a N/2 external clock period to thereby generating the synchronized N-bit data as a prefetched data.

Abstract: Methods and apparatus for maintaining cache coherency and reducing write-back traffic by using an enhanced MESI cache coherency protocol are disclosed. The enhanced MESI protocol includes the traditional MESI cache states (i.e., modified, exclusive, shared, invalid, and pending) as well as two additional cache states (i.e., enhanced modified and enhanced exclusive). An enhanced modified cache line is a cache line that is different than main memory and a copy of the cache line may be in another cache. An enhanced exclusive cache line is a cache line that is not modified and a copy of the cache line is in another cache in a modified state. Depending on the state of a victimized cache line, an internal inquiry may be issued to other caches and/or a write-back operation may be performed prior to victimizing the selected cache line.

Abstract: The present invention is a system, method and apparatus for self-tuning cache management. In a preferred aspect of the invention, a self-tuning cache can include a primary cache and at least two test caches. A first one of the test caches can have a cache size which is smaller than a size of the primary cache. A second one of the test caches can have a cache size which is greater than the size of the primary cache. A cache engine can be programmed to manage the primary cache and the test caches. importantly, a cache tuner can be coupled to the primary and test caches. The cache tuner can include a configuration for resizing the primary cache when one of the at least two test caches demonstrates cache performance which justifies resizing the primary cache.

Abstract: A method and system for booting up multiple PCI peripheral devices, such that the number of bootable PCI peripheral devices is not limited by the amount of computer system memory that is dedicated to storing executable boot code for the peripheral devices. The executable boot code is stored on a Read Only Memory (ROM) on each peripheral device. When a new PCI peripheral device begins to boot up, a check for available memory space in a ROM scan memory address space is performed. If there is not enough available room in the ROM scan memory address space for the new device's executable boot code, then a ROM scan detection logic pages an image of another peripheral device's executable boot code out of the ROM scan memory address space before storing the new device's executable boot code into the ROM scan memory address space.

Abstract: Various embodiments of systems and methods for performing volume-based incremental backups are disclosed. A method may involve generating a snappoint of a volume. The snappoint indicates which portions (e.g., blocks or extents) of the volume have been modified between a time at which the snappoint was generated and a time at which a subsequent snappoint was generated. The method may also involve accessing information mapping the file to the volume and, if the snappoint identifies as having been modified any blocks of the volume to which the file maps, copying those blocks from the subsequent snappoint to the backup device. Portions not identified as having been modified by the snappoint are not copied. Program instructions implementing such a method may be stored on a computer accessible medium.

Abstract: Special purpose heaps are created to store different classes of data to which different rules apply. A library of functions is provided which is designed to respect the different classes of rules that apply to the different heaps, by storing data only on a heap that is designated for use with the proper class of data, and by resisting the performance of actions on data in a heap that is inconsistent with the rules that apply to the heap. The use of plural heaps in this manner discourages programmer error in which an operation is performed on data that is inconsistent with the data, since the programmer would explicitly have to copy data from one heap to the other in order to perform the action. In one example, one heap is designated for the storage of secret data, and another heap is designated for general-purpose (non-secret) data.

Abstract: A system and a method are disclosed for creating a new partition. The technique includes initially allocating initially available sectors in a designated new partition area of a source partition to the new partition and subsequently allocating additional sectors in the designated new partition area of the source partition to the new partition that have subsequently become available.

Abstract: A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.

Abstract: A data copy method for a disk sub system that is equipped with a first storage apparatus including a first logic storage apparatus divided into a first region and a second region and a second storage apparatus including a second logic storage apparatus divided into a first region and a second region, the first logic storage apparatus and the second logic storage apparatus connecting to a host apparatus, wherein data on the first logic storage apparatus is copied to the second logic storage apparatus by an instruction from the host apparatus.

Abstract: A method for replacing cache lines in a computer system having a non-uniform set associative cache memory is disclosed. The method incorporates access latency as an additional factor into the existing ranking guidelines for replacement of a line, the higher the rank of the line the sooner that it is likely to be evicted from the cache. Among a group of highest ranking cache lines in a cache set, the cache line chosen to be replaced is one that provides the lowest latency access to a requesting entity, such as a processor. The distance separating the requesting entity from the memory partition where the cache line is stored most affects access latency.

Abstract: A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge in an order that can be different from the order of the corresponding client transactions. The command scheduler may also re-order memory access commands such as read and write. The slicing and out-of-order command scheduling allow a reduction in memory latency. The data transfer to and from clients can be kept in order.

Abstract: A storage controlling apparatus comprises a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and is to be written to a cache memory or a memory. The storage controlling apparatus further comprises a data storing unit which receives the store data from the store port, temporarily stores the store data, and comprised between the store port and the cache memory or the memory, and a data write controlling unit which controls a write of the store data from the store port to the data storing unit.

Abstract: The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shootdown data, different processors can describe the memory they want to free concurrently. Thus, concurrent TLB-shootdown request are less likely to result in performance-limiting TLB-shootdown contentions that have previously constrained the scaleability of multiprocessor systems.

Abstract: One embodiment is directed to the deletion of content units from a storage system. When a content unit is deleted, a reflection may be created and stored on the storage system. The reflection identifies the deleted content unit and may include additional information, such as a portion of the content of the content unit and audit information regarding the deletion of the content unit.

Abstract: An information handling system for mirroring data, in a fashion that is similar to asynchronous mirroring, but less complex in function. Source data storage for storing and updating data is provided, with first intermediate data storage, target data storage, second intermediate data storage, and mirroring control. The mirroring control conducts first cyclic incremental flashcopy of the source data storage, the beginning of each first cyclic incremental flashcopy comprising a consistency point. The first cyclic incremental flashcopy comprises copying data to be mirrored to the first intermediate storage and synchronously mirroring the data to the second intermediate data storage.