Abstract: One embodiment of a computer system has processors, having address spaces the processors can address directly. Each address space is directly linked to at least one other address space by memory within more than its own address space. The total size of the address spaces within the system linked together either directly or through directly linked address spaces is greater than the address space any resource within the system can address directly.

Abstract: A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.

Abstract: A software routine that writes downloaded updated operating system software over existing application code to flash memory of a cable modem in an inverted arrangement. If the download process is interrupted before the update can be verified, a pointer still points to the existing code to facilitate update-interruption recovery. After verifying a successful update, a new pointer is generated that points to the updated operating system. Then, updated application code can be downloaded and stored in the flash memory over the old operating system code. Thus, each time an update is performed, the location of the operating system within the flash memory with respect to the location of the application code is inverted. This allows the size of flash memory to be reduced, as only one copy of the operating system and application code must be stored, while retaining capability to recovery from an incomplete download.

Abstract: A system, apparatus, and method are disclosed for controlling accesses into memory to minimize sequential accesses to the same bank of memory, at least in part, by characterizing a subset of an address in parallel with address translations associated with those accesses. In one embodiment, an exemplary memory controller can include an address translator configured to translate an address useable by a processor to a first memory address. Also, the memory controller includes a bit characterizer configured to characterize a subset of the address as having a value from a range of values, and a bank separator coupled to the address translator and the bit characterizer for receiving a first portion of the first memory address and the value, respectively. Accordingly, the bank separator is configured to differentiate the first portion from a second portion of a second memory address.

Abstract: Techniques for implicitly caching connections to a resource (e.g., a database) are provided. A request for a connection does not specify that available connections are stored in a cache. If available connections are stored in a cache, the connection to the resource is obtained from the cache. Otherwise, a new connection to the resource is opened directly, without a connection caching mechanism.

Abstract: A method and a system is provided for persistently storing and restoring objects of an object oriented environment established on a computer system having a volatile memory and a persistent storage. Pieces of memory, referred to as segments are allocated in the volatile memory. Then, a first list is created that contains first references to said segments. The segments are further divided into blocks. The blocks are indicated by second references. The second references are stored in a second list. In order to store an object present in the volatile memory, a block is allocated. Then an object description is created by saving the object's values of its variables. After saving the object description in the allocated block, a new element is added to the second list containing the particular reference to said created object description. Then, the references of the object descriptions of all other objects referenced in the present object are determined.

Abstract: A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.

Abstract: The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit is coupled to an external peripheral by an external data bus. The integrated circuit has a processor coupled to an internal data bus. The system comprises the following. An external bus circuit is coupled to the internal and external data busses. The bus interface circuit is configured to receive read and write signals for data request data. In response, the bus interfaces circuit transmits a wait signal until data from the external peripheral is available on the internal data bus. The wait signal indicates that the external and internal data busses are not available for other purposes. After the processor has received or transmits the data, the bus interface circuit stops transmitting the wait signal and transmits a busy signal. The busy signal indicates that the internal data bus is available and the external data bus is not available for other purposes.

Abstract: One embodiment is a system for locating content on a storage system, in which the storage system provides a location hint to the host of where the data is physically stored, which the host can resubmit with future access requests. In another embodiment, an index that maps content addresses to physical storage locations is cached on the storage system. In yet another embodiment, intrinsic locations are used to select a storage location for newly written data based on an address of the data. In a further embodiment, units of data that are stored at approximately the same time having location index entries that are proximate in the index.

Abstract: The invention relates to a reproduction apparatus having a buffer for reducing the mean access time to an information carrier which has for example a discontinuous data structure or a relatively long access time. For writing sectors to the buffer and for finding sectors in the buffer, a control table with a number of place holders and three variables is provided, the place holders in each case pointing with an index to a subsequent place holder in an endless chain of place holders which is divided into three regions, in which a predetermined sector in the order in the respective region is identified by one of the variables. Even though only one row of place holders is provided, multiple access to a plurality of sectors written to the buffer is made possible with a low outlay by means of the control table, so that the number of slower accesses to the information carrier is reduced and the mean access time is shortened.

Abstract: A back-up power source and a back-up storage device are utilized to power a processor and a volatile memory device during a primary power failure. An emergency data-storage algorithm is invoked to create a table of modified data analogous to data residing in a non-volatile memory device associated with a different processor. This table of modified data is written to the back-up storage device.

Abstract: Historical access information identifies which resources in a storage area network access portions of shared storage in the storage area network. Based on an analysis of the historical access information, a management report generator application analyzing such information can infer the existence of a cluster of resources that access a common portion of shared storage. When the management report generator identifies that two or more resources access the same storage resources during approximately the same timeframe, the management report generator knows that there is a high likelihood that the two or more resources are part of a cluster sharing access to common storage resources. Thus, when reporting a tally of storage resources used in the storage area network, it is possible for the management report generator to take into account the cluster and indicate that two resources share access to a common portion of storage.

Abstract: A technique for controlling access to resources that may be accessed by one or more entities in a system. According to the technique, an entity accesses a shared resource by issuing a request containing an identifier that identifies the resource and an operation that specifies an operation to be performed on the resource. The operation is compared with one or more outstanding operations associated with the shared resource to determine if the operation conflicts with one or more of the outstanding operations. If a conflict is detected, a guard value is applied to determine if a race condition could occur. If a race condition is detected, the operation is blocked; otherwise, the operation is allowed.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. If information for responding to a request is available in a remote data cache, a response with a completion indicator is provided to the requesting processor. The completion indicator allows the request to be met without having to probe local or remote nodes.

Abstract: In a computer system that concurrently executes a plurality of tasks, a cache controller eliminates the possibility of the hit rate of one task dropping due to execution of another task. A region managing unit manages a plurality of regions in a cache memory in correspondence with a plurality of tasks. An address receiving unit receives, from a microprocessor, an address of a location in a main memory at which data to be accessed to execute one of the plurality of tasks is stored. A caching unit acquires, if the data to be accessed is not stored in the cache memory, a data block including the data from the main memory, and stores the acquired data block into a region in the cache memory corresponding to the task.

Abstract: In one embodiment, the present invention includes a cache memory having a plurality of cache lines to store data, in which at least some of the cache lines are adapted to store data in a compressed state. The cache memory also may include a first tag corresponding to each of the cache lines to indicate whether data in the corresponding cache line is compressible.

Abstract: A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose RAM before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides in the cache memory. The comparison may also be performed concurrently by a system controller device, which may abort the main memory access if a cache hit is detected.

Abstract: When copy instruction details are transferred to a first storage control unit from an application program, a channel processor captures the instruction details into local memory. Then, the instruction details are analyzed, and based on the analysis result, an open remote copy/MRCF instruction is output to an open remote copy/MRCF control section. If the instruction details have no problem, a response is made to a host unit that the writing response is normally made. To be ready for reading of inquiry information by the host unit, shared memory is searched for the inquiry information to create output data from the first storage control unit to the host unit. With such a structure, a storage device in a disk array apparatus external to another disk array apparatus can be used as resources of any device connectable to higher-level systems.

Abstract: A system and method for improving dynamic memory removals by reducing the file cache size prior to the dynamic memory removal operation initiating are provided. In one exemplary embodiment, the maximum amount of physical memory that can be used to cache files is reduced prior to performing a dynamic memory removal operation. Reducing the maximum amount of physical memory that can be used to cache files causes the page replacement algorithm to aggressively target file pages to bring the size of the file cache below the new maximum limit on the file cache size. This results in more file pages, rather than working storage pages, being paged-out.

Abstract: A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.