Abstract: A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

Abstract: An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.

Abstract: A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Abstract: A package combining a MEMS substrate, a CMOS substrate and another MEMS substrate in one package that is vertically stacked is disclosed. The package comprises a sensor chip further comprising a first MEMS substrate and a CMOS substrate with a first surface and a second surface and where the first MEMS substrate is attached to the first surface of the CMOS substrate. The package further includes a second MEMS substrate with a first surface and a second surface, where the first surface of the second MEMS substrate is attached to the second surface of the CMOS substrate and the second surface of the second MEMS substrate is attached to a packaging substrate. The first MEMS substrate, the CMOS substrate, the second MEMS substrate and the packaging substrate are provided with electrical inter-connects.

Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

Abstract: A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

Abstract: The light emitting device includes a first conductive semiconductor layer; a second conductive semiconductor layer on the first conductive semiconductor layer; and an active layer between the first and second conductive semiconductor layers. The active layer includes a plurality of well layers and a plurality of barrier layers, wherein the well layers include a first well layer and a second well layer adjacent to the first well layer. The barrier layers include a first barrier layer disposed between the first and second well layers, and the first barrier layer includes a plurality of semiconductor layers having an energy bandgap wider than an energy bandgap of the first well layer. At least two layers of the plurality of semiconductor layers are adjacent to the first and second well layers, and have aluminum contents greater than that of the other layer.

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Abstract: The present invention generally relates to a MEMS device and a method of manufacture thereof. The RF electrode, and hence, the dielectric layer thereover, has a curved upper surface that substantially matches the contact area of the bottom surface of the movable plate. As such, the movable plate is able to have good contact with the dielectric layer and thus, good capacitance is achieved.

Abstract: A finger metal oxide metal capacitor including an outer conducting structure and an inner conducting structure. The outer conducting structure is defined in a plurality of metal layers and a plurality of via layers of an integrated circuit and includes first and second side portions. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. Each of the outer conducting structure and the inner conducting structure includes respective finger sections extending in the plurality of metal layers. Oxide is arranged between the outer conducting structure and the inner conducting structure.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.

Abstract: A method of manufacturing a semiconductor device includes forming at least one sacrificial layer on a substrate during a complementary metal-oxide-semiconductor (CMOS) process. An absorber layer is deposited on top of the at least one sacrificial layer. A portion of the at least one sacrificial layer beneath the absorber layer is removed to form a gap over which a portion of the absorber layer is suspended. The sacrificial layer can be an oxide of the CMOS process with the oxide being removed to form the gap using a selective hydrofluoric acid vapor dry etch release process. The sacrificial layer can also be a polymer layer with the polymer layer being removed to form the gap using an O2 plasma etching process.

Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.

Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

Abstract: An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and the electrically conductive feed line, a second substrate on the insulating layer, and an antenna on the second substrate and having nanofilm layers stacked on the second substrate. The antenna is coupled to the feed line through an aperture.

Abstract: A light emitting diode including a substrate, a p-type and n-type semiconductor layers, an active layer, an interlayer, an electron barrier layer, a first and a second electrodes are provided. The n-type semiconductor layer is disposed on the sapphire substrate. The active layer has an active region with a defect density greater than or equal to 2×107/cm2. The active layer is disposed between the n-type and p-type semiconductor layers. The wavelength of light emitted by the active layer is ?, and 222 nm???405 nm. The active layer includes i quantum barrier layers and (i?1) quantum wells, each quantum well is disposed between any two quantum barrier layers, and i?2. N-type dopant is doped in at least k layers of the i quantum barrier layers, wherein k is a natural number and k?1, when i even, k?i/2, and when i is odd, k?(i?1)/2.

Abstract: A method of making a SiC buffer layer on a Si substrate comprising depositing an amorphous carbon layer on a Si(001) substrate, controlling the thickness of the amorphous carbon layer by controlling the time of the step of depositing the amorphous carbon layer, and forming a deposited film. A 3C—SiC buffer layer on Si(001) comprising a porous buffer layer of 3C—SiC on a Si substrate wherein the porous buffer layer is produced through a solid state reaction.