Patents Examined by Matthew Landau
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Patent number: 9673187Abstract: The disclosed technology relates to electronics, and more particularly, to protection devices that protect circuits from transient electrical events such as electrical overstress/electrostatic discharge. A protection device includes a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells. The device additionally includes a first PN diode formed in one of the at least two wells and having a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and includes a second PN diode formed in one of the at least two wells and having a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type. The device additionally includes a first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage.Type: GrantFiled: July 10, 2015Date of Patent: June 6, 2017Assignee: ANALOG DEVICES, INC.Inventors: Javier Alejandro Salcedo, Jonathan Pfeifer
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Patent number: 9673047Abstract: A method of making a SiC buffer layer on a Si substrate comprising depositing an amorphous carbon layer on a Si(001) substrate, controlling the thickness of the amorphous carbon layer by controlling the time of the step of depositing the amorphous carbon layer, and forming a deposited film. A 3C—SiC buffer layer on Si(001) comprising a porous buffer layer of 3C—SiC on a Si substrate wherein the porous buffer layer is produced through a solid state reaction.Type: GrantFiled: October 1, 2015Date of Patent: June 6, 2017Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Connie H. Li, Glenn G. Jernigan, Berend T. Jonker, Ramasis Goswami, Carl S. Hellberg
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Patent number: 9673321Abstract: An opening extending through a gate insulating layer and a gate conductor layer is formed in the circumferential portion of a Si pillar at an intermediate height of the Si pillar. A laminated structure including two sets each including a Ni film, a poly-Si layer containing donor or acceptor impurity atoms, and a SiO2 layer is formed so as to surround the opening. A heat treatment is carried out to form silicide from the poly-Si layers and this silicide formation causes the resultant NiSi layers to protrude and come into contact with the side surface of the Si pillar. The donor or acceptor impurity atoms diffuse from the NiSi layers into the Si pillar to thereby form an N+ region and a P+ region serving as a source or a drain of SGTs.Type: GrantFiled: July 22, 2015Date of Patent: June 6, 2017Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 9666779Abstract: A semiconductor light emitting diode chip relates to the field of production technologies of a light emitting diode. In the present invention, corresponding graphical current extension layers are respectively disposed below an N pad and a P pad, and in all light emitting compound areas, there is electronic compound light emitting. Compared with the prior art, an area of a light emitting compound area is increased, which can effectively improve current distribution and light emitting brightness of a chip. In addition, graphical current extension can effectively increase an adhesion of a pad on a surface and improve the reliability of a chip.Type: GrantFiled: March 13, 2014Date of Patent: May 30, 2017Assignee: Yangzhou Zhongke Semiconductor Lighting Co., Ltd.Inventors: Yuzhe Jin, Yaping Feng, Yi Zhang, Jiajia Li, Zhicong Li, Yijun Sun, Guohong Wang
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Patent number: 9666764Abstract: An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide multiple LED dies that are joined to a single carrier die. The multiple LED dies on the single carrier die are connected in series and/or in parallel by interconnection in the LED dies and/or in the single carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area. Related devices and fabrication methods are described.Type: GrantFiled: March 13, 2013Date of Patent: May 30, 2017Assignee: Cree, Inc.Inventors: Michael John Bergmann, Kevin Haberern, Alan Wellford Dillon
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Patent number: 9666711Abstract: A semiconductor device is provided. The semiconductor device includes a first conductive type substrate; a second conductive type body region disposed in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; a first conductive type first well region disposed in the second conductive type body region; a gate structure disposed over the top surface of the first conductive type substrate; a source region, wherein the source region includes a heavily-doped first conductive type source region and is disposed in the second conductive type body region; and a drain region, wherein the drain region is heavily doped first conductive type and is disposed in the first conductive type first well region.Type: GrantFiled: May 31, 2016Date of Patent: May 30, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Wen-Hsin Lin, Shin-Cheng Lin
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Patent number: 9660106Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.Type: GrantFiled: August 18, 2014Date of Patent: May 23, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wei Ta, Yi-Shan Chiu, Yuan-Hsiang Chang
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Patent number: 9659833Abstract: A semiconductor package includes an adhesive member disposed on a package substrate to have a trapezoid cross-section view, and a semiconductor chip disposed on the adhesive member and attached to the package substrate by the adhesive member. The semiconductor chip has a first surface and a second surface facing the first surface, and the second surface of the semiconductor chip contacts the adhesive member. The semiconductor chip includes a tension supplement pattern attached to the second surface and spaced apart from the package substrate.Type: GrantFiled: July 24, 2015Date of Patent: May 23, 2017Assignee: SK hynix Inc.Inventors: Dae Woong Lee, Tae Min Kang, Han Jun Bae
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Patent number: 9659893Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.Type: GrantFiled: August 14, 2015Date of Patent: May 23, 2017Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
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Patent number: 9653587Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.Type: GrantFiled: May 6, 2015Date of Patent: May 16, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hitoshi Matsuura
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Patent number: 9653341Abstract: A semiconductor structure includes a die including a first surface, a recess extended from an aperture disposed on the first surface and including a sidewall disposed within the die, and a polymeric member configured for filling and sealing the recess and including a first outer surface and a second outer surface, wherein the first outer surface is interfaced with the sidewall of the recess.Type: GrantFiled: March 5, 2014Date of Patent: May 16, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Chun Miao, Chao-Wen Shih, Shih-Wei Liang, Ching-Feng Yang
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Patent number: 9653489Abstract: There is provided a light emitting device including: a semiconductor substrate; a plurality of pixel circuits that is disposed in a display region of the semiconductor substrate; a first wiring that is formed of a conductive material so as to be supplied with a predetermined electric potential; and a plurality of first contact portions that is formed of a conductive material so as to connect the semiconductor substrate and the first wiring. The plurality of first contact portions and the first wiring are provided in the display region.Type: GrantFiled: January 29, 2014Date of Patent: May 16, 2017Assignee: SEIKO EPSON CORPORATIONInventors: Hitoshi Ota, Ryoichi Nozawa, Takeshi Nomura
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Patent number: 9653653Abstract: A light emitting diode device is provided. The light emitting diode device has a substrate, a plurality of metal pads, a plurality of LEDs and a first metal conductive wire. A plurality of first metal pads of the metal pads are disposed on a first surface of the substrate, and the LEDs are disposed on a part of the first metal pads. Each of the LEDs has at least one first electrode contact. The first electrode contact of each of the LEDs electrically connected to the first metal conductive wire has the same electrode contact polarity. Moreover, another light emitting diode device is also provided.Type: GrantFiled: June 30, 2015Date of Patent: May 16, 2017Assignee: Everlight Electronics Co., Ltd.Inventors: Wei-Ting Wu, Jun Yu Chen, Han-Hsiang Chiang
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Patent number: 9647009Abstract: A TFT array substrate structure includes a patterned metal light-shielding layer that includes a plurality of metal light-shielding blocks arranged in an array and a narrowed metal strip connected between two adjacent ones of the metal light-shielding blocks. The metal light-shielding layer and a common electrode are connected to and receive a common voltage signal. For each of TFT, the pixel electrode is connected to a drain electrode of the TFT; the pixel electrode has a portion overlapping the common electrode to form a first storage capacitor; and the metal light-shielding layer has a portion overlapping the drain electrode and the pixel electrode to form a second storage capacitor. The first storage capacitor and the second storage capacitor are connected in parallel to increase the capacity of the storage capacitor. The metal light-shielding layer is arranged in a light-shielded area and thus the modification thereof does not affect aperture ratio.Type: GrantFiled: March 30, 2016Date of Patent: May 9, 2017Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Yu Zhao, Zhandong Zhang
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Patent number: 9640614Abstract: An integrated device includes a semiconductor body including an STI insulating structure that laterally delimits first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. A power component, formed in the second active area, includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region. The insulating region is arranged between the body region and the drain-contact region and has a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.Type: GrantFiled: October 8, 2014Date of Patent: May 2, 2017Assignee: STMICROELECTRONICS S.R.L.Inventors: Alessandro Causio, Paolo Colpani, Simone Dario Mariani
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Patent number: 9640478Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.Type: GrantFiled: June 25, 2015Date of Patent: May 2, 2017Assignee: AOI ELECTRONICS CO., LTD.Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
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Patent number: 9640576Abstract: An image sensing device includes: an active layer with a plurality of photo-sensing elements; a color pattern disposed over one of the photo-sensing elements, wherein the color pattern has a color selected from the group consisting of red (R), green (G), and blue (B); a microlens disposed on the color pattern; and a transmissive pattern being adjacent to the color pattern and over another one of the photo-sensing elements, wherein the transmissive pattern includes a color filter portion and a microlens portion, and an absolute value of a difference of refractive indexes between the microlens and the color pattern is less than 0.3, and there is no difference of refractive indexes between the microlens portion and the color filter portion of the transmissive pattern.Type: GrantFiled: August 20, 2014Date of Patent: May 2, 2017Assignee: VISERA TECHNOLOGIES COMPANY LIMITEDInventors: Han-Lin Wu, Chieh-Yuan Cheng, Yu-Kun Hsiao, Huang-Jen Chen
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Patent number: 9640505Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer is formed such a portion of the solder resist layer and a portion of the first conductive trace collectively have a T-shaped cross section.Type: GrantFiled: August 13, 2015Date of Patent: May 2, 2017Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
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Patent number: 9634197Abstract: An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide multiple LED dies that are joined to a single carrier die. The multiple LED dies on the single carrier die are connected in series and/or in parallel by interconnection in the LED dies and/or in the single carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area. Related devices and fabrication methods are described.Type: GrantFiled: March 13, 2013Date of Patent: April 25, 2017Assignee: Cree, Inc.Inventors: Michael John Bergmann, Kevin Haberern, Alan Wellford Dillon
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Patent number: 9627512Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate having a top surface; a first doped region in proximity to the top surface; a non-doped region positioned in proximity to the top surface and adjacent to the first doped region, having a first width; a metal gate positioned over the non-doped region and over a portion of the first doped region, having a second width. The first width is smaller than the second width, and material constituting the non-doped region is different from material constituting the substrate.Type: GrantFiled: August 13, 2014Date of Patent: April 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Mu-Tsang Lin