Patents Examined by Matthew Reames
  • Patent number: 10236315
    Abstract: Provided is a solid-state image pickup element including: a sensor unit configured to generate an electrical signal in response to incident light; a color filter covering the sensor unit; and a lens configured to concentrate the incident light into the sensor unit via the color filter and formed by a laminated film made of a predetermined lens material. The lens is formed on the color filter without providing a planarization layer for removing a difference in level in the color filter.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 19, 2019
    Assignee: Sony Corporation
    Inventors: Yutaka Ooka, Shinji Miyazawa, Kensaku Maeda, Atsushi Yamamoto
  • Patent number: 10211212
    Abstract: A semiconductor device includes a substrate having a first active region; first and second gate electrodes disposed on the first active region; first, second and third impurity regions disposed in the first active region; first, second and third active contacts disposed on and connected to the first, second and third impurity regions; a first power line electrically connected to the first impurity region through the first active contact; and a first bit line electrically connected to the second and third impurity regions through the second and third active contacts. The first gate electrode and the first and second impurity regions form a first transistor of a first memory cell. The second gate electrode and the second and third impurity regions form a second transistor of a second memory cell. The second impurity region is a drain of the first and second transistors of the first and second memory cells.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Inhak Lee
  • Patent number: 10199273
    Abstract: A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Li Kuo, Yung-Chang Lin
  • Patent number: 10199470
    Abstract: A Field Effect Transistor (FET) having a substrate; a plurality of active regions disposed on the substrate; and a laterally extending finger-like control electrode disposed on a portion of a surface of the substrate. The active regions are laterally spaced one from the other successively along the laterally extending finger-like control electrode. The laterally extending finger-like control electrode controls a flow of carriers through each one of the plurality of active regions between a source electrode and a drain electrode.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: February 5, 2019
    Assignee: Raytheon Company
    Inventors: Alan J. Bielunis, Istvan Rodriguez, Christopher M. Laighton
  • Patent number: 10192980
    Abstract: The disclosure is directed to a high-electron mobility transistor that includes a SiC substrate layer, a GaN buffer layer arranged on the SiC substrate layer, and a p-type material layer having a length parallel to a surface of the SiC substrate layer over which the GaN buffer layer is provided. The p-type material layer is provided in one of the following: the SiC substrate layer and a first layer arranged on the SiC substrate layer. A method of making the high-electron mobility transistor is also disclosed.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: January 29, 2019
    Assignee: Cree, Inc.
    Inventors: Saptharishi Sriram, Alexander Suvorov, Christer Hallin
  • Patent number: 10186689
    Abstract: Embodiments of the invention provide an organic light-emitting display (OLED) panel and a manufacturing method for the OLED panel, which comprises providing a substrate comprising a first electrode layer which comprises a plurality of first electrodes spaced apart from each other, forming an insulating layer on the substrate, etching off the insulating layer over the first electrodes by a photolithography process to form a pattern of sub-pixel depositing areas and forming organic light-emitting layers for desired colors within the sub-pixel depositing areas, and forming a second electrode layer on the insulating layer and the organic light-emitting layers. Embodiments of the invention can exactly prepare the organic light-emitting layers to improve yield.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: January 22, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanzhao Li, Gang Wang, Li Sun
  • Patent number: 10186685
    Abstract: The present invention relates to a method for manufacturing a light extraction substrate for an organic light emitting diode, a light extraction substrate for an organic light emitting diode, and an organic light emitting diode comprising same, and more specifically, to a method for manufacturing a light extraction substrate for an organic light emitting diode, a light extraction substrate for an organic light emitting diode, and an organic light emitting diode comprising same, capable of significantly increasing light extraction efficiency of the organic light emitting diode.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 22, 2019
    Assignee: Corning Precision Materials Co., Ltd.
    Inventor: Joo Young Lee
  • Patent number: 10177064
    Abstract: The present disclosure relates to an air-cavity package, which includes a substrate, a base, and a semiconductor die. The substrate includes a substrate body, thermal vias extending through the substrate body, and a metal trace on a bottom side of the substrate body and separate from the thermal vias. The base includes a base body, a perimeter wall extending about a perimeter of the base body, and a signal via structure. Herein, the bottom side of the substrate body resides on the perimeter wall to form a cavity, and the signal via structure extends through the perimeter wall and is electrically coupled to the metal trace. The semiconductor die is mounted on the bottom side of the substrate body, exposed to the cavity, and electrically coupled to the metal trace. The thermal vias conduct heat generated from the semiconductor die toward a top side of the substrate body.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 8, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Kevin J. Anderson, Anthony Chiu, Tarak A. Railkar
  • Patent number: 10177275
    Abstract: An epitaxial structure and a method for making the same are provided. The epitaxial structure includes a substrate, an epitaxial layer and a carbon nanotube layer. The epitaxial layer is located on the substrate. The carbon nanotube layer is located in the epitaxial layer. The method includes following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is suspended above the epitaxial growth surface. An epitaxial layer is epitaxially grown from the epitaxial growth surface to enclose the carbon nanotube layer therein.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 8, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 10170372
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim
  • Patent number: 10170540
    Abstract: Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Christopher J. Penny, Theodorus E. Standaert, Junli Wang
  • Patent number: 10170641
    Abstract: A vertical positive-intrinsic-negative (pin) diode includes a semiconductor substrate in which a P-type region, an intrinsic region, and an N-type region are sequentially disposed in a vertical direction to be formed therein, a first electrode formed on one surface of the semiconductor substrate to be in electrical contact with the P-type region, and a second electrode formed on the other surface of the semiconductor substrate to be in electrical contact with the N-type region, wherein the P-type region and the N-type region are respectively disposed in an upper portion and a lower portion of the semiconductor substrate to be opposite to each other.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: January 1, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chulho Kim, Dong Seung Kwon, Bonghyuk Park, Young-Kyun Cho
  • Patent number: 10163739
    Abstract: A solid-state imaging device includes a substrate having a rectangular shape; a first region configured to extend on the substrate in a length direction of the substrate, and to include a plurality of electrode pads arranged above the substrate through a multilayer interconnection; and a second region configured to extend in the length direction, and to include an imaging element, an optical filter, and an insulating film. The second region extends on the substrate on which the imaging element is arranged. The optical filter is arranged above the substrate and faces the imaging element through the insulating film. The second region extends in parallel to the first region to be apart from the first region by a given distance. The plurality of electrode pads are arranged to be apart from each other by a given space, equal to or smaller than the given distance, in the length direction.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: December 25, 2018
    Assignee: Ricoh Company, Ltd.
    Inventors: Isamu Miyanishi, Tohru Kanno
  • Patent number: 10164054
    Abstract: A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: December 25, 2018
    Assignee: Qualcomm Incorporated
    Inventors: Bin Yang, Gengming Tao, Xia Li, Periannan Chidambaram
  • Patent number: 10163678
    Abstract: Forming a semiconductor structure by forming a plurality of trenches in a semiconductor material, forming a plurality of non-conductive structures in the plurality of trenches, and forming a doped region of the first conductivity type. The plurality of trenches are spaced apart from each other, have substantially equal depths, and include a first trench and a second trench. The plurality of non-conductive structures include a first non-conductive structure in the first trench and a second non-conductive structure in the second trench. The doped region is formed between the first non-conductive structure and the second non-conductive structure. No region of a second conductivity type lies horizontally in between the first non-conductive structure and the second non-conductive structure.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: December 25, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Sameer Pendharkar, Guru Mathur, Takehito Tamura
  • Patent number: 10157791
    Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
  • Patent number: 10158011
    Abstract: A trench gate type MOS gate structure is provided in an active region on a substrate front surface side, and a floating p-type region is provided in a mesa region between trenches. A groove is provided distanced from the trench in a surface layer on the substrate front surface side of the floating p-type region. A second gate electrode is provided across an insulation layer in the interior portion of the groove. The second gate electrode covers the surface on the substrate front surface side of the floating p-type region. Thus, the second gate electrode is embedded in a surface layer on the substrate front surface side of the floating p-type region between the floating p-type region and an interlayer dielectric, whereby the substrate front surface is flattened. Controllability of turn-on di/dt is high, mirror capacitance is low, and an element structure having an intricate pattern can be formed.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: December 18, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Onozawa, Takahiro Tamura
  • Patent number: 10157898
    Abstract: A light emitter, comprising a monolithic n-type layer (comprising at least first and second n-type regions), a monolithic p-type layer (comprising at least first and second p-type regions), at least a first isolation region and at least a first electrically conductive via that extends through at least part of the first isolation region. At least part of the first isolation region is between the first n-type region and the second n-type region, and/or least part of the first isolation region is between the first p-type region and the second p-type region.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 18, 2018
    Assignee: Cree, Inc.
    Inventors: Gerald H. Negley, Antony Paul Van De Ven
  • Patent number: 10153199
    Abstract: A method of fabricating a semiconductor device. The method includes forming source/drain features in a substrate on opposite sides of a gate structure, forming an etch stop layer over the source/drain features, and depositing a dielectric layer on the etch stop layer. The method further includes performing a first atomic layer etching (ALE) process having a first operating parameter value on the dielectric layer to form a first part of an opening, and performing a second ALE process having a second operating parameter value to extend the opening to expose the source/drain features. The first operating parameter value is different from the second operating parameter value.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Kei-Wei Chen, Lai-Wan Chong, Tsan-Chun Wang
  • Patent number: 10151034
    Abstract: A substrate processing apparatus includes a rotary table arranged in a vacuum chamber, a first reaction gas supply unit that supplies a first reaction gas to a surface of the rotary table, a second reaction gas supply unit that is arranged apart from the first reaction gas supply unit and supplies a second reaction gas, which reacts with the first reaction gas, to the surface of the rotary table, and an activated gas supply unit that is arranged apart from the first and second reaction gas supply units. The activated gas supply unit includes a discharge unit that supplies an activated fluorine-containing gas to the surface of the rotary table, a pipe that is arranged upstream of the discharge unit and supplies the fluorine-containing gas to the discharge unit, and at least one hydrogen-containing gas supply unit arranged at the pipe for supplying a hydrogen-containing gas into the pipe.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: December 11, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Shigehiro Miura