Abstract: An image sensor may include: a photoelectric conversion element including a second conductive layer formed over a first conductive layer; an insulating layer and a third conductive layer which are sequentially formed over the second conductive layer; an opening exposing the second conductive layer through the third conductive layer and the insulating layer; a channel layer formed along the surface of the opening, and including first and second channel layers which are coupled to each other while having different conductivity types; and a transfer gate formed over the channel layer to fill the opening, and partially formed over the third conductive layer.

Abstract: Measures are provided, by which mechanical stresses within the diaphragm structure of a MEMS component may be intentionally dissipated, and which additionally enable the implementation of diaphragm elements having a large diaphragm area in comparison to the chip area. The diaphragm element is formed in the layer structure of the MEMS component. It spans an opening in the layer structure and is attached via a spring structure to the layer structure. The spring structure includes at least one first spring component, which is oriented essentially in parallel to the diaphragm element and is formed in a layer plane below the diaphragm element. Furthermore, the spring structure includes at least one second spring component, which is oriented essentially perpendicularly to the diaphragm element. The spring structure is designed in such a way that the area of the diaphragm element is greater than the area of the opening which it spans.

Abstract: A fabricating method of a semiconductor light emitting device includes disposing a plurality of non-conductive walls on a substrate. An alignment position is formed between every two adjacent non-conductive walls. A plurality of semiconductor light emitting units on a first carrier board are respectively aligned to the alignment positions. The semiconductor light emitting units are divided into a plurality of groups. The semiconductor light emitting units in one of the groups are dissociated from the first carrier board. Thus, the semiconductor light emitting units in the group fall into the corresponding alignment positions due to gravity. Each of the semiconductor light emitting units is electrically connected with the substrate through a first electrode. A conductive layer is formed on the semiconductor light emitting units. Accordingly, the semiconductor light emitting units are electrically connected together to the conductive layer through second electrodes.

Abstract: A technique relates to a vertical device. A gate is embedded in a transparent substrate. A gate dielectric material is disposed on the gate. A nanotube film is disposed on the gate dielectric material. A quantum dot light emitting diode is disposed on a portion of the nanotube film.

Abstract: To provide a solid-state image sensing device or a semiconductor display device, which can easily obtain the positional data of an object without contact. Included are a plurality of first photosensors on which light with a first incident angle is incident from a first incident direction and a plurality of second photosensors on which light with a second incident angle is incident from a second incident direction. The first incident angle of light incident on one of the plurality of first photosensors is larger than that of light incident on one of the other first photosensors. The second incident angle of light incident on one of the plurality of second photosensors is larger than that of light incident on one of the other second photosensors.

Abstract: The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.

Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

Abstract: A method is provided. The method includes removing an extracted die including an original ball bond from a previous packaged integrated circuit, bonding the extracted die to an interposer to create a remapped extracted die, 3D printing one or more first bond connections between one or more original bond pads of the extracted die and one or more first bond pads of the interposer, securing the remapped extracted die to a package base, and 3D printing one or more second bond connections between one or more second bond pads of the interposer and one or more package leads or downbonds of the package base. The one or more first and second bond connections conform to the shapes and surfaces of the extracted die, the interposer, and the package base.

Abstract: Light emitting device includes structure protruding from a side of a surface of second conductive semiconductor layer of LED chip toward a side of a surface of second conductor portion of mounting substrate to contact the surface of second conductor portion, and is positioned to extend around an outer periphery of second electrode. First electrode and a first conductor portion are joined to each other by first joint portion, and second joint portion joining second electrode and second conductor portion to each other fills a space surrounded by second electrode, protruding structure, and second conductor portion. Protruding structure is disposed to extend around the outer periphery of second electrode to surround second joint portion in planar view. A part of mounting substrate overlapping protruding structure in planar view is either identical in height to or lower than a part of second conductor portion joined to second joint portion.

Abstract: A method of manufacturing an organic light-emitting display includes a first mask process forming an active layer of a TFT and a refractive layer on a substrate, forming a DBR layer covering the active and refractive layers, a second mask process forming a gate electrode and a first electrode unit on the DBR layer, forming an interlayer insulation layer covering the gate electrode and the first electrode unit, a third mask process forming contact holes in the interlayer insulation layer and the DBR layer exposing portions of the active layer and a hole exposing the first electrode unit, a fourth mask process forming source and drain electrodes on the interlayer insulation layer that contact the active layer via the contact holes, and forming a pixel electrode from the first electrode unit, and a fifth mask process forming a pixel definition layer exposing the pixel electrode.

Abstract: A semiconductor structure includes a substrate, at least one first epitaxial layer, and at least one second epitaxial layer. The substrate has a plurality of recesses multidimensionally arranged therein. The first epitaxial layer is disposed at least in the recesses of the substrate. The second epitaxial layer is disposed on the first epitaxial layer.

Abstract: A semiconductor structure configured for use in a VCSEL or RCLED. The semiconductor structure includes an oxidizing layer constructed from materials that can be oxidized during a lithographic process so as to create an oxide aperture. The semiconductor structure further includes a number of layers near the oxidizing layer. A passivation material is disposed on the layers near the oxidizing layer. The passivation material is configured to inhibit oxidation of the layers.

Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.

Abstract: A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract: A display device includes a flexible substrate having a display area for displaying an image, and a pad area adjacent the display area, a circuit film coupled to the flexible substrate at the pad area, and a passivation layer on at least a part of the circuit film and at part of the pad area.

Abstract: A semiconductor device includes a semiconductor body having first and second opposing surfaces, a first isolation layer on the first surface of the semiconductor body, and an electrostatic discharge protection structure. The electrostatic discharge protection structure includes a diode structure on the first isolation layer, a first terminal and a second terminal. The diode structure includes a polysilicon layer having first regions and at least one second region of opposite conductivity type alternatingly arranged along a first lateral direction between the first terminal and the second terminal. The diode structure extends from an electrostatic discharge protection part into an edge termination part along a second lateral direction. A first breakdown voltage associated with the diode structure in the electrostatic discharge protection part is smaller than a second breakdown voltage associated with the diode structure in the edge termination part.

Abstract: A light emitting device package may be provided that includes: a lead frame; a light emitting device disposed on the lead frame; a metallic reflector which is disposed on the lead frame, has a hollow portion in which the light emitting device is disposed, reflects light emitted from the light emitting device, and is formed by a mold; and a resin body which surrounds the lead frame and the reflector. The resin body includes an insulation layer disposed between the lead frame and the reflector, and a protrusion disposed on the reflector.

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

Abstract: A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and conductive bumps disposed on the first conductive patterned layer. Each conductive bump has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, and the first dimension is greater than the second dimension. A semiconductor package structure includes the semiconductor substrate, at least one die electrically connected to the conductive bumps, and a molding compound encapsulating the conductive bumps.