Patents Examined by Matthew Whipple
  • Patent number: 6593245
    Abstract: A method for plasma etching of silicon nitride using a mixture of trifluoromethane and oxygen in a ratio of approximately 8 to 1 to selectively etch silicon nitride in preference to silicon dioxide and photoresist, resulting in critical dimension gain.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: July 15, 2003
    Assignee: Advanced Micro Devices
    Inventor: Maria Chan
  • Patent number: 6444480
    Abstract: A semiconductor device fabrication apparatus includes a thermal treatment device for thermally processing a semiconductor substrate, a first oxygen monitor for monitoring the density of oxygen in said thermal treatment device, a load-lock chamber separably coupled to said thermal treatment device for housing the semiconductor substrate before thermal treatment thereof by said thermal treatment device, and a second oxygen monitor for monitoring the density of oxygen in said load-lock chamber. First, the semiconductor substrate is introduced into the load-lock chamber, and then the load-lock chamber is evacuated. Thereafter, the density of oxygen in the load-lock chamber is measured by the second oxygen monitor, and the thermal treatment device is evacuated, after which the density of oxygen in the thermal treatment device is measured by the first oxygen monitor.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: September 3, 2002
    Assignee: Sony Corporation
    Inventor: Masaki Saito
  • Patent number: 6235563
    Abstract: An improved polycrystalline or polysilicon film having large grain size, such as 1 &mgr;m to 2 &mgr;m in diameter or greater, is obtained over the methods of the prior art by initially forming a silicon film, which may be comprised of amorphous silicon or micro-crystalline silicon or contains micro-crystal regions in the amorphous phase, at a low temperature via a chemical vapor deposition (CVD) method, such as by plasma chemical vapor deposition (PCVD) with silane gas diluted with, for example, hydrogen, argon or helium at a temperature, for example, in the range of room temperature to 600° C. This is followed by solid phase recrystallization of the film to form a polycrystalline film which is conducted at a relatively low temperature in the range of about 550° C. to 650° C. in an inert atmosphere, e.g., N or Ar, for a period of about several hours to 40 or more hours wherein the temperature is gradually increased, e.g., at a temperature rise rate below 20° C./min, preferably about 5° C.
    Type: Grant
    Filed: November 7, 1991
    Date of Patent: May 22, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Hideaki Oka, Satoshi Takenaka, Masafumi Kunii
  • Patent number: 6168980
    Abstract: A low temperature process for fabricating a high-performance and reliable semiconductor device in high yield, comprising forming a silicon oxide film as a gate insulator by chemical vapor deposition using TEOS as a starting material under an oxygen, ozone, or a nitrogen oxide atmosphere on a semiconductor coating having provided on an insulator substrate; and irradiating a pulsed laser beam or an intense light thereto to remove clusters of such as carbon and hydrocarbon to thereby eliminate trap centers from the silicon oxide film. Also claimed is a process comprising implanting nitrogen ions into a silicon oxide film and annealing the film thereafter using an infrared light, to thereby obtain a silicon oxynitride film as a gate insulator having a densified film structure, a high dielectric constant, and an improved withstand voltage.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: January 2, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang
  • Patent number: 6140215
    Abstract: Method and apparatus are disclosed for low temperature deposition of CVD and PECVD films utilizing a gas-dispersing showerhead position within one inch of a rotating substrate. The showerhead is positioned a suitable distance below a gas-dispensing apparatus such as a steady stay flow of gas develops between the ring and showerhead. A cylindrical structure extends between the gas-dispersing ring and a showerhead to contain the gas over the showerhead yielding a small boundary layer over the substrate to ensure efficient uniform deposition of a film on a substrate surface. In the one embodiment of the present invention the showerhead is bias with RF energy such that it acts as an electrode to incite a plasma proximate with the substrate for PECVD. The cylinder is isolated from the showerhead such as by a quartz insulator ring to prevent ignition of a plasma within the cylinder, or alternatively, the cylinder is fabricated of quartz material.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: October 31, 2000
    Assignee: Tokyo Electron Limited
    Inventors: Robert F. Foster, Joseph T. Hillman, Rikhit Arora
  • Patent number: 6133050
    Abstract: A precursor solution formed of a liquid polyoxyalkylated metal complex in as solvent is applied to a substrate in the formation of a metal oxide thin film. The liquid thin film is baked in air to a temperature up to 500.degree. C. while UV radiation having a wavelength ranging from 180 nm to 300 nm is applied. The thin film can be twice-baked at increasing temperatures while UV radiation is applied at one or both bakings. The film is then annealed at temperature ranging from about 700.degree. C. to 850.degree. C. to produce a thin-film solid metal oxide product. Alternatively, the UV radiation may be applied to the liquid precursor, the thin film may be annealed with UV radiation, or combinations of such applications of UV radiation to the precursor, to the thin film before or after baking, and/or UV annealing may be used. The use of UV radiation significantly reduces the leakage current and carbon impurity content of the final metal oxide.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: October 17, 2000
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Masamichi Azuma, Larry D. McMillan, Carlos A. Paz de Araujo, Michael C. Scott
  • Patent number: 6130164
    Abstract: A semiconductor device having a gate oxide layer formed by selective removal of the gate oxide layer and a process for manufacturing such a device is disclosed. A gate oxide layer is formed on a substrate. The gate oxide layer is selectively removed in a controlled ambient to reduce the thickness of the gate oxide layer. A gate electrode is disposed on the gate oxide layer. In accordance with one particular aspect of the process, the controlled ambient includes an NF.sub.3 bearing gas, which is flowed over the gate oxide layer to remove portions of the oxide layer.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: October 10, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, Mark C. Gilmer
  • Patent number: 6130118
    Abstract: A process for depositing a film at a high rate and with superior step coverage properties, which comprises installing a pair of electrodes crossing with another pair of electrodes making a right angle with respect to the another pair, and applying a high frequency power differing in phase to the electrodes in order to apply a high frequency power having a Lissajous' waveform in the reaction space during the deposition of a film on a substrate.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: October 10, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6130152
    Abstract: This invention pertains generally to precursors and deposition methods suited to aerogel thin film fabrication. An aerogel precursor sol which contains an oligomerized metal alkoxide (such as TEOS), a high vapor pressure solvent (such as ethanol) and a low vapor pressure solvent (such as water and 1-butanol) is disclosed. By a method according to the present invention, such a precursor sol is applied as a thin film to a semiconductor wafer, and the high vapor pressure solvent is allowed to evaporate while evaporation of the low vapor pressure solvent is limited, preferably by controlling the atmosphere adjacent to the wafer. The reduced sol is then allowed to gel at a concentration determined by the ratio of metal.alkoxide to low vapor pressure solvent. One advantage of the present invention is that it provides a stable, spinnable sol for setting film thickness and providing good planarity and gap fill for patterned wafers.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: October 10, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas M. Smith, Gregory P. Johnston, William C. Ackerman, Shin-Puu Jeng, Bruce E. Gnade
  • Patent number: 6127261
    Abstract: A method of depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other intermediate steps are performed.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: October 3, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Darin A. Chan
  • Patent number: 6124186
    Abstract: A method or producing hydrogenated amorphous silicon on a substrate, comprising the steps of: positioning the substrate in a deposition chamber at a distance of about 0.5 to 3.0 cm from a heatable filament in the deposition chamber; maintaining a pressure in said deposition chamber in the range of about 10 to 100 millitorr and pressure times substrate-filament spacing in the range of about 10 to 100 millitorr-cm, heating the filament to a temperature in the range of about 1,500 to 2,000.degree. C., and heating the substrate to a surface temperature in the range of about 280 to 475.degree. C.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: September 26, 2000
    Assignee: Midwest Research Institute
    Inventors: Edith C. Molenbroek, Archie Harvin Mahan, Alan C. Gallagher
  • Patent number: 6110820
    Abstract: A CMP process using two or more stages wherein each stage has a different polishing rate. The CMP process is characterized by a final stage that is longer in duration than performed in the prior art. In a particular example the final stage is approximately equal in duration to the initial stage. Alternatively, the final stage is performed so as to polish to depth sufficient to remove scratches created at the inititiation of the final polishing. Scratches initiated at the beginning of the final stage of polishing are removed by the extended length of time of the later stage of polishing.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: August 29, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Sujit Sharan
  • Patent number: 6107168
    Abstract: In the manufacture of semiconductor components, a SiC single crystal is exposed, during storage or transport between two process steps, to an oxygen-containing gas atmosphere, for example air. In order to prevent an oxide coating from forming on the SiC surface of the SiC single crystal, a carbon coating which does not react chemically with oxygen, preferably a graphite coating, is produced on said SiC surface.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: August 22, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventor: Roland Rupp
  • Patent number: 6096597
    Abstract: In one embodiment, the present invention provides a method of treating a dielectric layer 24. First, the dielectric layer is heated while being subjected to an O.sub.2 plasma. After that, the dielectric layer is heated while being subject to an ozone environment. This method can be useful in forming a capacitor 12 dielectric 24. In turn, the capacitor could be used in a DRAM memory device.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: August 1, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Tsu, William R. McKee, Shimpei Iijima, Isamu Asano, Masato Kunitomo, Tsuyoshi Tamaru
  • Patent number: 6087196
    Abstract: A method of fabricating semiconductor devices using ink-jet printing is provided to directly deposit patterned polymer films to create OLED's and other semiconductor devices. The luminescence of poly-vinylcarbazol (PVK) films, with dyes of coumarin 6 (C6), coumarin 47 (C47), and nile red was similar to that of films of the same composition deposited by spin-coating. Light emitting diodes with low turn-on voltages were also fabricated in PVK doped with C6 deposited by ink-jet printing.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: July 11, 2000
    Assignee: The Trustees of Princeton University
    Inventors: James C. Sturm, Chung Chih Wu, Duane Marcy, Thomas R. Hebner
  • Patent number: 6087208
    Abstract: A method for fabricating a MOSFET device is provided. The method includes a step of fining a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be over source/drain extension regions of the device; and the second gate oxide material is formed over a channel region of the device. The first gate oxide material has a low dielectric constant and provides for mitigating gate fringing field effects. The second gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device. Controlled uniform growth of the second gate oxide material is facilitated because of the thickness thereof.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: July 11, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Srinath Krishnan, Geoffrey Choh-Fei Yeap, Matthew Buynoski
  • Patent number: 6077754
    Abstract: A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, said silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: June 20, 2000
    Inventors: Anand Srinivasan, Sujit Sharan, Gurtej S. Sandhu
  • Patent number: 6077733
    Abstract: A new method is provided to manufacture a T-shaped gate. A layer of insulation is deposited over a semiconductor surface (typically the surface of a substrate), a dual damascene structure containing a via opening and a conducting line trench is created in the layer of insulation. A layer of sacrificial oxide is grown and subsequently removed (preventing initial surface defects and providing protection during subsequent steps of etching). A layer of gate oxide is selectively grown on the bottom of the dual damascene opening. A layer of poly is deposited over the layer of insulation thereby including the dual damascene opening, the poly is planarized down to essentially the top of the dual damascene structure and the insulation is removed from above the surface of the substrate in the regions surrounding the dual damascene structure leaving the dual damascene structure in place.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: June 20, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yen-Ming Chen, Wei-Jen Liu, Shih-Chi Lin, Kuo-Chou Liu
  • Patent number: 6074885
    Abstract: A method for constructing a device having a bottom electrode in contact with a layer of a ferroelectric dielectric material. In the method of the present invention, a layer of a field ferroelectric material is deposited on a substrate and etched to form a trench in which the bottom electrode is constructed. The bottom electrode is then deposited and a layer of the ferroelectric dielectric material is deposited over the bottom electrode and at least a portion of the field ferroelectric material. The ferroelectric layers are deposited in a perovskite state. These layers are etched back to the substrate in those areas that are outside of the device.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: June 13, 2000
    Assignee: Radiant Technologies, Inc
    Inventors: Leonard L. Boyer, Joseph T. Evans, Jr., Naomi B. Velasquez
  • Patent number: 6071797
    Abstract: In a method of forming an amorphous carbon thin film with a plasma chemical vapor deposition method, at least one of a hydrocarbon gas and a carbon fluoride gas is supplied in a reaction chamber as a material gas. By applying a high voltage between two electrodes, a plasma is generated in the reaction chamber using the supplied material gas. As a result, an amorphous carbon thin film is deposited on a substrate while preventing deposition of an adhesion on an inner wall of the reaction chamber. In order to prevent the adhesion from depositing on the inner wall, a bias voltage such as one of DC bias, a high frequency bias and a high frequency bias imposed on a DC bias is applied to the electrically conductive reaction chamber.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: June 6, 2000
    Assignee: NEC Corporation
    Inventors: Kazuhiko Endo, Toru Tatsumi