Patents Examined by Matthew Whipple
  • Patent number: 5904550
    Abstract: A method of preparing a semiconductor device, comprising: forming an amorphous silicon layer on a substrate, and applying shots of an excimer laser beam to the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer having a plurality of silicon grains, each of the grains having a grain size and including a crystallite having a crystallite size on the (111) plane, an average value of the crystallite sizes on the (111) plane of the crystallites included in the polysilicon layer being sixty percent or greater of an average value of the grain size.
    Type: Grant
    Filed: November 19, 1996
    Date of Patent: May 18, 1999
    Assignee: Casio Computer Co., Ltd.
    Inventor: Michiya Yamaguchi
  • Patent number: 5905044
    Abstract: A mass manufacturing method of semiconductor acceleration and vibration sensors uses a dispensing method, a electrical plating method, a screen-printing method or a preforming method in manufacturing a mass made of metal pastes in a desired size and amount on a mass pad of a thin metal film which is formed on a beam in a given pattern, so that it can be adapted to the mass-production of the sensors having the mass of the desired amount and size.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: May 18, 1999
    Assignees: Kyungpook National University Technology Research Center, Mando Machinery Corporation
    Inventors: Jong Hyun Lee, Woo Jeong Kim
  • Patent number: 5902122
    Abstract: A method of manufacturing a semiconductor device is provided. A first interlayer insulating layer is formed on a silicon substrate, and a lower metal layer is formed on the first interlayer insulating layer. A first insulating layer is formed on the first interlayer insulating layer including the lower metal layer, moisture contained in the first insulating layer is removed by N.sub.2 or N.sub.2 O plasma. Thereafter, a SOG layer and a second insulating layer are sequentially formed on the first insulating layer.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: May 11, 1999
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Dong Sun Sheen, Jeong Rae Lee
  • Patent number: 5899752
    Abstract: A method of in-situ cleaning a native oxide layer from the surface of a silicon wafer positioned in a vacuum chamber that is substantially free of oxidizing species by passing at least one non-oxidizing gas over the native oxide layer at a wafer cleaning temperature between about 650.degree. C. to about 1025.degree. C. for a sufficient length of time until such native oxide layer is removed.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: May 4, 1999
    Assignee: Applied Materials, Inc.
    Inventors: H. Peter W Hey, David Carlson
  • Patent number: 5899746
    Abstract: A base is etched using as mask a first masking layer which has been patterned, softened and deformed. Then, the first masking layer is eroded, a second masking layer is selfaligningly formed only on bare portions of the base, and the base is again etched using as mask the second masking layer. Within a pitch of the first masking layer, the base can thus be etched in two regions which are separated from each other. These treatments can also be conducted in two directions.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: May 4, 1999
    Assignee: Sony Corporation
    Inventor: Mikio Mukai
  • Patent number: 5899702
    Abstract: Methods for measuring the surface area of a top region of a silicon wafer by initially depositing a monolayer of hexamethyldisilizane over the surface area of the silicon wafer. The silicon wafer is then positioned within a vacuum environment. Next, oxygen is introduced into the vacuum chamber so that the HMDS substantially reacts with the oxygen to form products such as carbon dioxide and water. At least one of the water and the carbon dioxide are measured from the known volume of the vacuum chamber. Based on the amount of product formed, the amount of HMDS covering the surface area is determined. Finally, from the amount of HMDS calculated to be originally positioned on the surface area, a value for the surface area is determined.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: May 4, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Michael Nuttall, Kelly Hurley
  • Patent number: 5894064
    Abstract: A method of forming a thin film of a metal oxide on a substrate by coating the substrate with a solution comprising metal-organic precursors is disclosed. This method is applicable to, e.g., forming thin films of perovskite-phase titanates, zirconates, and/or niobates of divalent metals such as Ba, Sr, Pb and/or Ca. In one embodiment, a first precursor comprises a divalent metal coordinated to one or more organic ligands, and a second precursor comprises a tetravalent metal coordinated to one or more organic ligands are supplied in a common solution. A substrate 14 is coated with this solution (e.g. by spin coating) to form a preliminary thin film 10. Substrate heater 22 preferably heats substrate 14 to a temperature sufficient to react ligands from the first and second precursors in an ester elimination reaction which forms a volatile precursor 16. This reaction leaves an intermediate compound film 12 comprising the divalent metal and the tetravalent metal on the substrate.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: April 13, 1999
    Inventors: Mark Hampden-Smith, James Caruso, Clive Chandler
  • Patent number: 5891747
    Abstract: A method is presented to produce a change in the optical path length in the gap between two single mode optical fibers proportional to the lateral displacement of either fiber end normal to its axis. This is done with the use of refraction or diffraction at the interface between a guiding and non-guiding media to change the direction of propagation of the light in the gap. A method is also presented for laying a waveguide on a cantilever so that the displacement of the tip of the cantilever produces a proportional path length change in the gap by distancing the waveguide from the neutral axis of the cantilever. The fiber is supported as a cantilever or a waveguide is deposited on a micromachined cantilever and incorporated in an interferometer which is made totally on a silicon substrate with the use of integrated-optic technology.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: April 6, 1999
    Inventor: John Farah
  • Patent number: 5891800
    Abstract: An improved method for depositing a flow fill layer of an integrated circuit. Two flowlayers and two cap layers are deposited. The wafer is warmed between the deposition of the first cap layer and the deposition of the second flowlayer, to evaporate water from the first flowlayer. Preferably, each of the cap layers is deposited in two separate steps of plasma enhanced chemical vapor deposition, to inhibit crack formation in the flowlayers. Most preferably, after the depositions of each flowlayer, the flowlayer is planarized by flowing H.sub.2 O.sub.2 thereupon.
    Type: Grant
    Filed: May 28, 1997
    Date of Patent: April 6, 1999
    Assignee: Tower Semiconductor Ltd.
    Inventors: Coren Ben-Guigui, Jeff Levy, Zmira Lavie
  • Patent number: 5885905
    Abstract: A method of processing a semiconductor substrate includes the step of subjecting a semiconductor substrate to a heat treatment under a gaseous atmosphere. The method comprises the step of subjecting a semiconductor substrate to a heat treatment at temperatures not lower than 1100.degree. C. under a non-oxidizing atmosphere, wherein heat treatments before said heat treatment applied to the semiconductor substrate are applied under heat treating temperatures and heat treating time which fall within a region defined by a line connecting four points of (900.degree. C., 4 minutes), (800.degree. C., 40 minutes), (700.degree. C., 11 hours) and (600.degree.0 C., 320 hours) in a graph, in which the heat treating temperature is plotted on the abscissa and the heat treating time is plotted on the ordinate of the graph.
    Type: Grant
    Filed: January 4, 1996
    Date of Patent: March 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Souichi Nadahara, Kikuo Yamabe, Hideyuki Kobayashi, Kunihiro Terasaka, Akihito Yamamoto, Naohiko Yasuhisa
  • Patent number: 5882978
    Abstract: A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, said silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: March 16, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Anand Srinivasan, Sujit Sharan, Gurtej S. Sandhu
  • Patent number: 5880029
    Abstract: A method of passivating semiconductor devices including the steps of providing a semiconductor device having a surface of semiconductor material to be passivated, exposing the surface of semiconductor material to deep ultra-violet (DUV) radiation in an ambiance including oxygen so as to form a layer of oxide on the surface of semiconductor material, and forming a layer of passivation material on the layer of oxide. The DUV oxide forms a different interface with the semiconductor material which significantly improves operating characteristics of the semiconductor device.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: March 9, 1999
    Assignee: Motorola, Inc.
    Inventors: Kurt Eisenbeiser, Jenn-Hwa Huang
  • Patent number: 5880040
    Abstract: A new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N.sub.2 O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si--SiO.sub.2 interface than either N.sub.2 O oxynitride or nitridation of SiO.sub.2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N.sub.2 O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: March 9, 1999
    Assignee: Macronix International Co., Ltd.
    Inventors: Shi-Chung Sun, Chun-Hon Chen, Lee-Wei Yen, Chun-Jung Lin
  • Patent number: 5880041
    Abstract: A method for forming a dielectric layer on a surface of a substrate uses high pressure. A pressure vessel of a high pressure oxidation equipment is heated to a predetermined temperature. The substrate is placed inside the pressure vessel. The pressure vessel is pressurized to a pressure above atmospheric pressure. A flow of an oxidizing gas and a flow of steam are introduced into the pressure vessel, wherein the steam flow is only a fraction of the oxidizing gas flow. The dielectric layer on the surface is formed through an oxidizing reaction of the oxidizing gas and steam with the surface of the substrate, wherein the flow of steam acts in a catalytic-like manner to parabolicly accelerate the oxidizing reaction at the surface.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: March 9, 1999
    Assignee: Motorola Inc.
    Inventor: T. P. Ong
  • Patent number: 5880003
    Abstract: For giving a device surface to a semiconductor device comprising a semiconductor substrate portion which has a substrate surface and a protruding portion protruding from the substrate surface, a method includes the steps of coating the substrate surface and the protruding portion with a first anti-polishing film, depositing an insulator film on the first anti-polishing film, and coating the insulator film with a second anti-polishing film. The insulator film has a first polishing rate for a polishing operation. The second anti-polishing film has a second polishing rate which can be slower than the first polishing rate for the polishing operation. Thereafter, the polishing operation is applied to the second anti-polishing film and to the insulator to make the device surface become substantially planarized. It is preferable that the first anti-polishing film has the second polishing rate for the polishing operation.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: March 9, 1999
    Assignee: NEC Corporation
    Inventor: Yoshihiro Hayashi
  • Patent number: 5874350
    Abstract: A method for forming a functional silicon- or germanium-containing amorphous deposited film on a substrate which comprises a film-forming chamber having a film-forming space, a substrate holder and an electric heater for positioning the substrate in the film-forming chamber, an exhaust pipe in fluid communication with the film-forming chamber, a first gas-introducing portion for providing an active species (H), having an activation space for generating the active species (H), a microwave discharge supply source and a passage for providing a gaseous hydrogen-containing material into the activation space in order to produce the active species (H), a second gas-introducing portion for providing a gaseous silicon- or germanium-containing material (X), capable of reacting with the active species (H) to form a reaction product (HX) that is capable of forming the functional deposited film on the substrate, and a transportation path having a mixing space and a second microwave discharge energy supply source for promo
    Type: Grant
    Filed: October 13, 1994
    Date of Patent: February 23, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventor: Katsumi Nakagawa
  • Patent number: 5874368
    Abstract: A process for the low pressure chemical vapor deposition of silicon nitride from ammonia and a silane of the formula: (t-C.sub.4 H.sub.9 NH).sub.2 SiH.sub.2 provides improved properties of the resulting film for use in the semiconductor industry.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: February 23, 1999
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Ravi Kumar Laxman, David Allen Roberts, Arthur Kenneth Hochberg, Herman Gene Hockenhull, Felicia Diane Kaminsky
  • Patent number: 5874356
    Abstract: The present invention discloses a method for forming a zig-zag bordered opening in a semiconductor structure such that the film stress in a barrier/glue layer of TiN can be significantly reduced to eliminate the occurrence of volcano defect in which delamination or peeling-off of the TiN layer from the contact opening occurs. The method can be easily carried out by providing a mask that has a desirable zig-zag pattern during a photomasking step performed on the semiconductor device.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: February 23, 1999
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: C. H. Chen, Y. C. Chao, Y. M. Tsui, W. R. Chang
  • Patent number: 5872065
    Abstract: An Si--O--F insulating film having a low dielectric constant is deposited on a substrate by thermally reacting disassociated SiF.sub.4 radicals and ozone or oxygen gas in a vacuum chamber. The SiF.sub.4 radicals are formed remotely from the chamber and interact thermally with the ozone or oxygen without requiring plasma enhancement. The deposited Si--O--F film has good gap-filling properties and is suitable for forming IMD layers over high aspect ratio 0.25 micron geometries.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: February 16, 1999
    Assignee: Applied Materials Inc.
    Inventor: Visweswaren Sivaramakrishnan
  • Patent number: 5869405
    Abstract: At least both a rapid thermal etch step and a rapid thermal oxidation step are performed on a semiconductor substrate in situ in a rapid thermal processor. A method including an oxidation step followed by an etch step may be used to remove contamination and damage from a substrate. A method including a first etch step followed by an oxidation step and a second etch step may likewise be used to remove contamination and damage, and a final oxidation step may optionally be included to grow an oxide film. A method including an etch step followed by an oxidation step may also be used to grow an oxide film. Repeated alternate in situ oxidation and etch steps may be used until a desired removal of contamination or silicon damage is accomplished.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: February 9, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Randhir P.S. Thakur