Abstract: The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is then formed in the recess. The process is continued with a formation of a second insulative layer, a potion of which is removed to form an opening exposing a portion of the barrier layer. An oxidation resistant conductive layer is deposited in the recess and forms at least a portion the storage node electrode of the capacitor.

Abstract: A method for forming the dielectric layer of a capacitor. A titanium layer and a tantalum pentoxide layer are sequentially formed over a polysilicon lower electrode. A high-temperature treatment is performed so that titanium in the titanium layer and silicon in the polysilicon lower electrode react to form a titanium silicide layer at their interface. Titanium in the titanium layer also reacts with oxygen in the atmosphere to form a titanium oxide layer at its interface with the tantalum pentoxide layer. The titanium silicide layer, the titanium oxide layer and the tantalum pentoxide layer together constitute a composite dielectric layer with a high dielectric constant capable of increasing the capacitance of the capacitor.

Abstract: A semiconductor process in which a silicon film is chemically vapor deposited upon a native oxide film as part of the gate oxide formation process. The invention contemplates a method of forming a thin gate dielectric semiconductor transistor. A semiconductor substrate which includes a native oxide film on an upper region of a silicon bulk is provided and a silicon film is deposited on the native oxide film. A first oxide film is then formed on a the native oxide film by thermally oxidizing a portion of the silicon film proximal to the native oxide film such that the thin gate dielectric comprises the native oxide film and the first oxide film. Thereafter, a conductive gate is formed on the thin gate dielectric and a pair of source/drain structures are formed within a pair of source/drain regions of the semiconductor substrate. The pair of source/drain structures are laterally displaced on either side of the channel region of the semiconductor substrate.

Abstract: The present invention provides a method of inter-poly oxide (IPO) layer underlying a polysilicon resistor in a memory product. The IPO layer 15 is formed by a modified low pressure SACVD-O.sub.3 -TEOS process that gives the IPO layer a smoother surface and good planarization. This IPO layer gives the overlying polysilicon resistors a more uniform resistance. The method begins by providing a semiconductor structure 10. Next, in an important step, an inter-poly oxide (IPO) layer 11 is formed using low pressure ozone assisted sub-atmospheric chemical vapor deposition (SACVD O.sub.3 -TEOS) process at a pressure between about 20 and 150 torr. A polysilicon resistor 15 is then formed on said inter-poly oxide (IPO) layer. The memory device is completed by forming passivation and conductive layers thereover.

Abstract: A process for forming a nanoporous dielectric coating on a substrate. The process includes either (i) combining a stream of an alkoxysilane composition with a stream of a base containing catalyst composition to form a combined composition stream; immediately depositing the combined composition stream onto a surface of a substrate and exposing the combined composition to water (in either order or simultaneously); and curing the combined composition; or (ii) combining a stream of an alkoxysilane composition with a stream of water to form a combined composition stream; immediately depositing the combined composition stream onto a surface of a substrate; and curing the combined composition.

Abstract: An apparatus and method for forming thin film aerogels on semiconductor substrates is disclosed. It has been found that in order to produce defect.about.free nanoporous dielectrics with a controllable high porosity, it is preferable to substantially limit evaporation and condensation of pore fluid in the wet gel thin film, e.g. during gelation, during aging, and at other points prior to obtaining a dried gel. The present invention simplifies the atmospheric control needed to prevent evaporation and condensation by restricting the atmosphere in contact with the wet gel thin film to an extremely small volume. In one embodiment, a substrate 26 is held between a substrate holder 36 and a parallel plate 22, such that a substantially sealed chamber 32 exists between substrate surface 28 and chamber surface 30. Preferably, the average clearance between surfaces 28 and 30 is less than 5 mm, or more preferably, less than 1 mm.

Abstract: The invention provides a semiconductor device in which interlayer insulative layers are composed of amorphous carbon film. The amorphous carbon film may include fluorine (F) therein. The invention further provides a method of fabricating a semiconductor device including an interlayer insulative layer composed of amorphous carbon film including fluorine (F), the method having the step of carrying out plasma-enhanced chemical vapor deposition (PCVD) using a mixture gas including (a) at least one of CF.sub.4, C.sub.2 F.sub.6, C.sub.3 F.sub.8, C.sub.4 F.sub.8 and CHF.sub.3, and (b) at least one of N.sub.2, NO, NO.sub.2, NH.sub.3 and NF.sub.3. The method provides amorphous carbon film having superior heat resistance and etching characteristics. By composing interlayer insulative layers of a semiconductor device of the amorphous carbon film, the semiconductor device can operate at higher speed.

Abstract: This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO.sub.2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO.sub.2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO.sub.2 interface. The entire synthesis is done under low-pressure (e.g., 0.

Abstract: Deep groove structure for semiconductors comprising a semiconductor substrate, a groove or a cavity formed in said semiconductor substrate and a suspending glass membrane formed on the groove or deep cavity, prepared by a flame hydrolysis deposition process. The suspending glass membrane functions as a planarization structure and has surface at the same level of the surface of the semiconductor substrate. The present invention also discloses a method to prepare the deep groove structure.

Abstract: A method of fabricating an interpolysilicon dielectric structure in a non-volatile memory includes the steps of forming a high dielectric constant layer 12 on a floating gate 10 and an oxynitride layer 14 on the high dielectric constant layer 12. A control gate 18 may be formed on the oxynitride layer 14 to produce a dual gate structure with a high capacitance and therefore a high coupling ratio.

Abstract: A method for growing a dielectric film containing Sr on a substrate includes the steps of: dissolving a Sr compound containing Sr((CH.sub.3).sub.5 C.sub.5).sub.2 into an organic solvent or mixing Sr(thd).sub.2 and an amine compound to form a source material; vaporizing the source material to produce a gaseous source material; and decomposing the gaseous source material, obtained in the step of vaporization, in the vicinity of a surface of a substrate held in a reaction chamber, to cause a deposition of a dielectric film containing Sr upon the surface of the substrate.

Abstract: A wafer having a recess with an aspect ratio of 0.5 or above on a surface to be processed is placed on a holder provided within a process chamber. A process gas consisting of a mixture of a material gas of SiH.sub.4 and a carrier gas of H.sub.2 is uniformly supplied to the surface of the wafer vertically. The pressure within the process chamber is set at 1 Torr or above. The temperature of the surface to be processed of the wafer is set at 600.degree. C. to 800.degree. C. Under these conditions, a polysilicon film is formed in the recess by a vapor phase growth method. During the formation of the film, the wafer is rotated at 500 rpm or above by an output of a motor via a holder. Thereby, a high film formation rate and a good step coverage can be made compatible.

Abstract: A local interconnection to a device region in/on a substrate is formed by depositing either silicon oxynitride or silicon oxime as an etch stop layer, at a temperature of less than about 480.degree. C. to increase the hot carrier injection (HCI) lifetime of the resulting semiconductor device. A dielectric layer is then deposited over the etch stop layer and through-holes are etched exposing the etch stop layer using a first etching process. A second etching process is then conducted, which etches through the etch stop layer exposing at least one device region. The resulting through-hole is then filled with conductive material(s) to form a local interconnection.

Abstract: This invention relates to a method for forming a low barrier height oxide layer on the surface of a crystalline silicon substrate, comprising: (A) forming spaced field oxide regions on the surface of said crystalline silicon substrate, the space between said field oxide regions comprising a tunnel region; (B) vapor depositing a layer of amorphous silicon on the surface of said field oxide regions and on the surface of said substrate in said tunnel region, the thickness of said layer of amorphous silicon being in the range of about 50 .ANG. to about 100 .ANG.; and (C) oxidizing said layer of amorphous silicon. The oxidized amorphous silicon layer in said tunnel region is a tunnel oxide layer and, in one embodiment, the inventive method includes the step of (D) forming a floating gate over said tunnel oxide layer, said tunnel oxide layer having a barrier height of about 1.6 to about 2.0 eV.

Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, O--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH.sub.3 flow, decreasing the SiH.sub.4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.

Abstract: A method and apparatus for improving film stability of a halogen-doped silicon oxide layer. The method includes the step of introducing helium along with the process gas that includes silicon, oxygen and a halogen element. Helium is introduced at an increased rate to stabilize the deposited layer. In a preferred embodiment, the halogen-doped film is a fluorosilicate glass film and TEOS is employed as a source of silicon in the process gas. In still another preferred embodiment, SiF.sub.4 is employed as the fluorine source for the FSG film.

Abstract: The present invention relates to tinoxide thin film, a process for manufacturing thereof comprising the step of depositing tin while providing oxygen or ionized oxygen around a substrate, and relates to a gas detecting sensor prepared by the use of such tinoxide thin film.

Abstract: A method and an apparatus for depositing a dielectric layer to fill in a gap between adjacent metal lines. In preferred embodiments of the method, a first dielectric layer is deposited over the lines and subsequently etched using both chemical and physical etchback steps. After the etchback steps are completed, a second dielectric layer is deposited over the first dielectric layer to fill in the gap.

Abstract: A process is provided for forming sharp asperities, useful as field emitters. The process comprises: patterning and doping a silicon substrate. The doped silicon substrate is anodized. The anodized area is then used for field emission tips. The process of the present invention is also useful for low temperature sharpening of tips fabricated by other methods. The tips are anodized, and then exposed to radiant energy, and the resulting oxide is removed.

Abstract: In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).