Abstract: Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).

Abstract: Cache memory systems and methods thereof are provided. A first example cache memory system may include a central processing unit (CPU) and a first memory, a second memory positioned between the CPU and the first memory and storing at least one block of the first memory and a block quantity determination unit which determines a block quantity indicating a number of blocks of the first memory to be stored in the second memory. A second example cache memory system, including a cache memory receiving a request to provide data associated with an input address, determining whether the input address is included in the cache memory, loading a plurality of adjacent data blocks, associated with the input address, from the main memory if the input address is not included within the cache memory.

Abstract: A cache memory system includes a cache memory and a block replacement controller. The cache memory may include a plurality of sets, each set including a plurality of block storage locations. The block replacement controller may maintain a separate count value corresponding to each set of the cache memory. The separate count value points to an eligible block storage location within the given set to store replacement data. The block replacement controller may maintain for each of at least some of the block storage locations, an associated recent access bit indicative of whether the corresponding block storage location was recently accessed. In addition, the block replacement controller may store the replacement data within the eligible block storage location pointed to by the separate count value depending upon whether a particular recent access bit indicates that the eligible block storage location was recently accessed.

Abstract: A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Abstract: Representative is a computer-implemented method of detecting a buffer overflow condition. In accordance with the method, a destination address for a computer process' desired right operation is received and a determination is made as to whether the destination address is within an illegitimate writable memory segment within the process' virtual address space (VAS). If so, the process is preferably alerted of the potential buffer overflow condition. A determination may also be made as to whether the destination address is legitimate, in which case the process may be informed of the memory segment which corresponds to the destination address.

Abstract: A message memory (1) with a flexible association between the message-object memories of the message memory (2) and the segments of a physical memory (3). The association is made through configuration, wherein one or more memory segments form a cluster as a function of the length of the message content to be stored.

Abstract: A method for automatically detecting an attempted invalid access to a memory address in accordance with an exemplary embodiment is provided. The method includes reading a first data set having a software application name and a memory address stored therein utilizing the mainframe computer. The memory address indicates a portion of a memory that is not allowed to be changed. The method further includes detecting when a software application is attempting to access the memory address and setting a first bit in the memory to a first value in response to the detection utilizing the mainframe computer. The method further includes storing a name of the software application, the memory address, and contents of the portion of the memory specified by the memory address, in a second data set, when the first bit has the first value utilizing the mainframe computer. The method further includes displaying an error message on a display device when the first bit has the first value.

Abstract: A method for storage management is provided which displays the materials on which it is determined which of the thin provisioning volume or the logical unit (LU) is to be used for storage promotion. The method is executed in a computer system having one or more host computers, one or more storage subsystems, and a management computer. The storage subsystem includes a physical disk and a disk controller. The disk controller provides the host computer with the thin provisioning volume. The management computer obtains the allocated capacity from the disk controller and the host-recognized capacity from the host computer. By subtracting the obtained allocated capacity from the host-recognized capacity, the management computer calculates an improved capacity. By dividing the calculated improved capacity by the obtained host-recognized capacity, the management computer calculates an improvement ratio and displays the calculated improvement ratio.

Abstract: Methods and systems for managing computer system configuration data are provided. The method includes staging the configuration data in a staging memory accessible to a first application, selecting a path for a transfer of the configuration data from the staging memory to a target memory, emulating a hardware data loader using a second software application adapted to control a transfer of the configuration data from the staging memory to the target memory, and transferring the configuration data from the staging memory to the target memory using the emulator. The method further effectively expands a memory capacity of a Flight Management Computer by providing swappable memory capacity such that a re-certification to Federal Aviation Administration standards of the Flight Management Computer is not triggered.

Abstract: A method for page random write and read in blocks of flash memory is disclosed. The data could be random written in the pages of block. The pages would be arranged when the block was filled with data, so as to prevent from data copied and erased repeatedly. Present invention would reduce the data read/write time and increase the life-span of flash memory.

Abstract: In bit alterable memories, a particular header of a particular block may be programmed to a particular code to indicate that the block is to be considered empty. This saves the time of resetting all the bits in both the header and the data section of the block.

Abstract: Various embodiments of systems and methods are disclosed for performing online backup and restore of volume configuration information. In some embodiments, a method involves receiving a request to restore a volume configuration and, in response to the request, writing volume configuration information to a storage device. The volume configuration information includes a first disk signature, which identifies the storage device.

Abstract: A system to locate a storage device. The system receives a request for a data item stored on a first and second storage device. The request includes a data identifier for the data item. Next, the system generates a start value and a step value based on the data identifier. Next, the system locates the first storage device utilizing the start value and identifies the first storage device is unavailable. Next, the system locates a second storage device utilizing a backup value that is generated based on the step value and the start value.

Abstract: The present invention is to provide a method of specifying access sequence of a storage device, wherein queues with different priority are created in the storage device for recording access requests from at least one server at the front-end of the storage device to manage the access operation, and are recorded corresponding to the front-end servers and the priority thereof respectively via a priority table. When the front-end server makes an access request, the request will be added to the corresponding queue according to the source front-end server, and each queue will be processed according to the priority thereof. The maximum workload of the access request processed every single time of each queue is set respectively. Thus, the access requests of the queues with higher priority will be processed within a shorter time.

Abstract: A method and system for using writeable page tables to increase performance of memory address translation in computing environments utilizing a hypervisor. Guest operating systems are given temporary write-access to a page table page after the system confirms that such page is not part of the current address space (i.e., confirming that the page is part of a different page table from the one that is currently in use, such as a different user-space process). Alternatively, if the page is part of the currently running page table, the system invalidates the appropriate entry in the root page directory, thus “unlinking” it, and ensuring that the appropriate region of virtual address space is flushed from the translation lookaside buffer (TLB) in the current CPU and others that may be using it. After giving the OS write-access, the page is added to a validation queue.

Abstract: A virtualization system, upon judging that a write operation from a higher-level device is an operation to write in the format of the virtual volume, even when the write position of the write operation is in a virtual area different from a virtual area to which an allocated actual area has been allocated, if there is an unused area in the allocated actual area, writes management information to the unused area according to the write operation, and if there is no unused area in the allocated actual area, newly allocates an unallocated actual area, and writes management information to the newly allocated actual area according to the write operation.

Abstract: A disk snapshot acquisition method, which is applied in a server comprising a memory allocated with a kernel space and a hard disk, comprises the steps of allocating all chunks having data stored as a disk volume in said hard disk; allocating a first portion and a second portion in said hard disk; establishing a snapshot pointer in said kernel space, said snapshot pointer pointing to a starting address of said first portion in said hard disk; and when original data in one of said chunks of said disk volume is to be modified, duplicating said original data to a chunk in said second portion as backup data, then modifying said original data into modified data, and storing a piece of mapping information comprising an address of said modified data and an address of said backup data corresponding to said modified data to a copy-on-write table in said first portion.

Abstract: A computer system including a first storage system connected to a first host computer, a second storage system connected to a second host computer and a third storage system connected to the first and second storage systems. The second storage system sets transfer setting before an occurrence of a failure, the transfer setting being provided with a dedicated storage area to be used for transferring data to the third storage system by asynchronous copy in response to a failure at the first host computer. Before the start of data transfer between the second storage system and third storage system to be executed after an occurrence of the failure, the second storage system checks the dedicated storage area, data transfer line and transfer setting information, and if an abnormal state is detected, this abnormal state is reported to the host computer as information attached to the transfer setting.

Abstract: A caching mechanism implementing a “soft” Instruction-Most Recently Used (I-MRU) protection scheme whereby the selected I-MRU member (cache line) is only protected for a limited number of eviction cycles unless that member is updated/utilized during the period. An update or access to the instruction restarts the countdown that determines when the cache line is no longer protected as the I-MRU. Accordingly, only frequently used Instruction lines are protected, and old I-MRU lines age out of the cache. The old I-MRU members are evicted, such that all the members of a congruence class may be used for data. The I-MRU aging is accomplished through a counter or a linear feedback shift register (LFSR)-based “shootdown” of I-MRU cache lines. The LFSR is tuned such that an I-MRU line will be protected for a pre-established number of evictions.

Abstract: A modular data and storage management system. The system includes a time variance interface that provides for storage into a storage media of data that is received over time. The time variance interface of the modular data and storage management system provides for retrieval, from the storage media, of an indication of the data corresponding to a user specified date. The retrieved indication of the data provides a user with an option to access specific information relative to the data, such as content of files that are included in the data.