Abstract: A method and apparatus for receiving data at a non-solid state storage device, which includes a store cache and a storage medium. The received data is written to the store cache and transferred from the store cache to the storage medium. In response to receiving a signal at the storage device that is indicative of a power off condition of a data source device from which the data was received, at least a portion of the data remaining in the store cache is transferred to the storage medium prior to powering off the storage device.

Abstract: A system and method for determining a disk ownership model to be utilized by a storage system is disclosed. The storage system and method determines the individual disk ownership of each accessible disk to the storage system. If the number of disks utilizing a first ownership model is exceeded, the storage system utilizes the first ownership model. Otherwise, the storage system utilizes a second ownership model.

Abstract: A method and system are provided for selectively deleting data stored to storage media, such as a tape, in a network storage system. An instruction to delete selected data is received and the location of the data selected for deletion is identified. The location of the data is obtained by consulting an index of storage data. The selected data is retrieved, together with any other data on the tape that precedes the selected data. The retrieved data, excluding the selected data, is copied to a tape. The index is updated to reflect the changes in the stored data on the tape.

Abstract: An information processing apparatus according to the present invention comprises a communication device, a volatile memory for storing a communication data therein, a first CPU for controlling communication processings of the communication device and the communication data stored in the volatile memory, a ROM memory in which a program of the first CPU is previously stored, a second CPU for controlling the whole apparatus, a non-volatile memory for storing a whole program of the second CPU therein, a ROM memory in which another program executable by the second CPU is previously stored; and an external input terminal adapted in such a manner that if program execution by the second CPU starts in the non-volatile memory or in the ROM memory is selectively set, wherein where the program execution starts is selected in accordance with the setting of the external input terminal when activated, and a rewriting program for the whole program of the non-volatile memory is stored in the ROM memory.

Abstract: A method and apparatus for breaking complex X86 segment operations and segmented memory addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.

Abstract: A system, method, apparatus, and computer-readable medium are provided for expanding the data storage capacity of a virtualized storage system, such as a storage cluster. According to one method, maps are generated and stored that define a stripe pattern for storing data on the storage nodes of a storage cluster. The stripe pattern for each map is defined such that when a storage node is added to a cluster and the data is re-striped according to the new map, only the data that will subsequently reside in the new storage node is moved to the new storage cluster during re-striping. The stripe pattern may be further defined so that during re-striping no movement of data occurs between two storage nodes that existed in the cluster prior to the addition of the new storage node. The stripe pattern may be further defined such that during re-striping an equal amount of data is moved from each of the storage nodes that existed in the cluster prior to the addition of the new storage node to the new storage node.

Abstract: A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit.

Abstract: In a clustered processing system, replication logic controls replication of object data to one of more replica instances. Correction logic generates correction data based on the object data and generates code words by combining the object data and the correction data. The code words are transmitted to the one or more replica instances such that correctable errors in the object data can be corrected without re-transmission of the object data.

Abstract: Provided is a storage apparatus operable to prevent incomplete backup and perform efficient backup even in systems characterized by a relatively small backup window and high degrees of utilization by users. This storage apparatus performs a snapshot of a volume storing data, using a logoff or login request at a certain point in time within in the backup window as a trigger, and creates a replication volume of the volume based on the acquired snapshot. To achieve the data consistency, when a login request is made, the storage apparatus temporarily suspends processing for establishing a session until the snapshot is created, and resumes such processing for establishing the session based on a login request after the snapshot is created. In one implementation, the replication volume is created in the background.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A method for generating a consistent point in time copy of data, the method includes: selecting at least one selected data block to be copied from a source volume to a target volume in response to a request to generate a consistent point in time copy of multiple data blocks; waiting until the source volume is ready to send the at least one selected data block to a remote volume while queuing at least one data block modify request; de-queuing the at least one queued modify requests while copying the at least one selected data block from the source volume to the target volume; wherein the copying includes utilizing a first copying mechanism to copy a first selected data block if a request to modify the first selected block is de-queued before the first selected data block is copied to the target volume; else, the copying includes using a second copying mechanism that is slower than the first copying mechanism.

Abstract: Disclosed is a technique for data synchronization. A first identifier for a portion of data on a primary volume is determined, wherein a unique identifier is associated with each portion of data at the primary volume. A second identifier for a portion of corresponding data at a secondary volume is determined, wherein a unique identifier is associated with each portion of data at the secondary volume. The first and second identifiers are compared. When the first and second identifiers do not match, the portion of corresponding data at the secondary volume in a storage device is replaced with the portion of data at the primary volume.

Abstract: A technique places content, such as data, of one or more data containers on volumes of a striped volume set (SVS). The placement of data across the volumes of the SVS allows specification of a deterministic pattern of fixed length. That is, the pattern determines a placement of data of a data container that is striped among the volumes of the SVS. The placement pattern is such that the stripes are distributed exactly or nearly equally among the volumes and that, within any local span of a small multiple of the number of volumes, the stripes are distributed nearly equally among the volumes. The placement pattern is also substantially similar for a plurality of SVSs having different numbers of volumes.

Abstract: A multiprocessor system includes a plurality of microprocessors configured to operate on a plurality of operating systems, respectively, and a memory section configured to have a plurality of memory spaces respectively allocated to the plurality of microprocessors. Each of the plurality of microprocessors may include a translation look-aside buffer (TLB) and a page table register. The TLB stores a copy of at least a part of data of one of the plurality of memory spaces corresponding to the microprocessor, and the copy includes a relation of each of virtual addresses of a virtual address space and a corresponding physical address of a physical address space as the memory space. The page table register refers to the TLB in response to an execution virtual address generated based on an application program to be executed by the microprocessor to determine an execution physical address corresponding to the execution virtual address.

Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

Abstract: A method and system for locating and eliminating orphan files within a secondary storage device. The method includes identifying a secondary file on a secondary storage device, the secondary file being associated with file identification data, wherein the file identification data includes a content address, identifying a placeholder file on a primary storage device, the placeholder file being associated with an offline reference, and determining if the offline reference of the placeholder file validly references the content address of the secondary file.

Abstract: The present invention discloses a method for processing cache data, which is used in a dual redundant server system having a console end and a redundant control end. The console end mirrors a cache data saved in the console end into a mirrored cache data and sends the mirrored cache data to the redundant control end through a transmission unit. If the console end determines that the redundant control end cannot save the mirrored cache data, the console end will flush the cache data into a hard disk installed at the console end.

Abstract: A swap space is provided for a host computer system, where the swap space includes a plurality of swap files with each individual swap file for swapping data only for a single corresponding virtual machine (VM). The per-VM swap space is used solely by the single, corresponding VM, such that only that particular VM's memory is allowed to be swapped out to the swap file.

Abstract: In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for shortening the memory access latency using a snoop and cache copy tag information. When the local node's cache copy tag information is available, the memory access latency can be shortened by omitting a process to count snoop results. When memory position information is used to update the cache copy tag during cache replacement, it is possible to increase a ratio to hit a copy tag during reaccess from the local node.

Abstract: It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration such as in creating or deleting a volume or LUN, contents of the alteration are reflected in the database of iSNS or SLP. Also, in response to a change in setting of LUN masking, a discovery domain of iSNS or attribute values of SLP are updated so that the host computer can discover the disk volume. Also, objects and services are reregistered periodically according to a registration period of iSNS or lifetime of SLP to prevent registered contents from expiring.