Abstract: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Abstract: A computer system including a first storage system connected to a first host computer, a second storage system connected to a second host computer and a third storage system connected to the first and second storage systems. The second storage system sets transfer setting before an occurrence of a failure, the transfer setting being provided with a dedicated storage area to be used for transferring data to the third storage system by asynchronous copy in response to a failure at the first host computer. Before the start of data transfer between the second storage system and third storage system to be executed after an occurrence of the failure, the second storage system checks the dedicated storage area, data transfer line and transfer setting information, and if an abnormal state is detected, this abnormal state is reported to the host computer as information attached to the transfer setting.

Abstract: A method and computer program product for defining a multicast group within a local area network. The multicast group includes a storage initiator device, a plurality of storage targets, and one or more coded targets. A write request for storing a data segment within the multicast group is received on the storage initiator device. The data segment is multicast to the plurality of storage targets and the one or more coded targets included within the multicast group. A unique data chunk of the data segment is stored on each of the plurality of storage targets. A unique coded chunk of the data segment is generated and stored on each of the one or more coded targets.

Abstract: A system, method and computer program product for receiving on a non-volatile, solid-state, cache memory system, a data segment, including a plurality of data elements, from one or more of a volatile, solid-state, cache memory system and a non-volatile, electromechanical memory system. The data segment may be stored on the non-volatile, solid-state, cache memory system. Each data element includes one or more data extents.

Abstract: A swap space is provided for a host computer system, where the swap space includes a plurality of swap files with each individual swap file for swapping data only for a single corresponding virtual machine (VM). The per-VM swap space is used solely by the single, corresponding VM, such that only that particular VM's memory is allowed to be swapped out to the swap file.

Abstract: A method and computer program product for defining a multicast group within a local area network. The multicast group includes a storage initiator device and a plurality of storage targets. Each of the plurality of storage targets includes a storage index that identifies one or more data segments stored on the storage target. A write request for storing a data segment within the multicast group is received on the storage initiator device. A “check exist” message is generated that defines the data segment to be stored within the multicast group. The “check exist” message is multicast to the plurality of storage targets included within the multicast group.

Abstract: The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access.

Abstract: A modular data and storage management system. The system includes a time variance interface that provides for storage into a storage media of data that is received over time. The time variance interface of the modular data and storage management system provides for retrieval, from the storage media, of an indication of the data corresponding to a user specified date. The retrieved indication of the data provides a user with an option to access specific information relative to the data, such as content of files that are included in the data.

Abstract: A wear leveling method for a flash is provided, wherein the flash memory includes a plurality of physical blocks grouped into at least a data area and a spare area. The method includes setting a first predetermined threshold value as a wear-leveling start value and randomly generating a random number as a memory erased count, wherein the random number is smaller than the wear-leveling start value. The method also includes counting the memory erased count each time when the physical blocks are erased and determining whether the memory erased count is smaller than the wear-leveling start value, wherein a physical blocks switching is performed between the data area and the spare area when the memory erased count is not smaller then the wear-leveling start value. Accordingly, it is possible to uniformly use the physical blocks, so as to effectively prolong a lifetime of the store system.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A network device determines the presence of the pre-specified string in a message based on a sequence matching rule. A sequence represents non-contiguous portions of the message. A combination of content addressable memory, programmable processing units, and the programmable control unit may determine the presence of the pre-specified string in the message by comparing the non-contiguous portions of the message. Such an approach may reduce the computational resources required for searching the pre-specified string in the message.

Abstract: A method of locating a storage device of a number of storage devices is provided. A request for a data item is received. The request includes a globally unique identifier (GUID) that is associated with a user. A start number is generated based on the GUID, and the storage device that stores the data item is located based on the start number. The data item is then read from the located storage device. Other techniques for locating a storage device are also described.

Abstract: A data storage device and a method of operating the same include firmware recognizing that the data storage device has a smaller than normal capacity or includes a routine in the firmware when the number of bad blocks exceeds the maximum. Therefore, even if the number of bad blocks exceeds the maximum, the data storage device having a capacity smaller than the normal capacity can be used.

Abstract: Code, data, and/or other information types, may be isolated from one another and stored in distinct regions within the memory array of a nonvolatile memory. The distinct regions in memory may have corresponding read/write interfaces that are optimized for each information type.

Abstract: A virtualization system, upon judging that a write operation from a higher-level device is an operation to write in the format of the virtual volume, even when the write position of the write operation is in a virtual area different from a virtual area to which an allocated actual area has been allocated, if there is an unused area in the allocated actual area, writes management information to the unused area according to the write operation, and if there is no unused area in the allocated actual area, newly allocates an unallocated actual area, and writes management information to the newly allocated actual area according to the write operation.

Abstract: A method and apparatus for storing data on a computer data storage system are described. Two or more computers are coupled together to form a cluster of computers. One or more data storage devices are coupled to the two or more computers. One or more volumes of data storage devices are implemented on a plurality of computers of the two or more computers, where each volume is a logical arrangement of the one or more storage devices coupled to a selected computer of the plurality of computers. A data container holds data stored by the data storage system. The data container is striped over a plurality of the one or more volumes of data storage devices, whereby data stored in the data container is striped over a plurality of the volumes of data storage devices.

Abstract: A cache-aware Bloom filter system segments a bit vector of a cache-aware Bloom filter into fixed-size blocks. The system hashes an item to be inserted into the cache-aware Bloom filter to identify one of the fixed-size blocks as a selected block for receiving the item and hashes the item k times to generate k hashed values for encoding the item for insertion in the in the selected block. The system sets bits within the selected block with addresses corresponding to the k hashed values such that accessing the item in the cache-aware Bloom filter requires accessing only the selected block to check the k hashed values. The size of the fixed-size block corresponds to a cache-line size of an associated computer architecture on which the cache-aware Bloom filter is installed.

Abstract: A data storage device that performs a process of writing to a memory a plurality of measured data sets received in time series includes: a nonvolatile memory divided in a plurality of blocks to which the measured data is written; and a write control section that performs a processing including successively writing N sets of the measured data to a given block in the nonvolatile memory, and then successively writing next N sets of the measured data to another block, wherein the write control section judges whether or not the N sets of measured data lastly written to the given block of the nonvolatile memory and another N sets of measured data obtained after the N sets of measured data lastly written to the given block contain data with a value outside a predetermined range, writes new measured data to the given block such that the N sets of measured data lastly written to the given block are not overwritten when the data with a value outside the predetermined range is included, and writes new measured data to t