Abstract: In a method of managing a cache directory in a memory system, an original system address is presented to the cache directory when corresponding associativity data is allocated to an associativity class in the cache directory. The original system address is normalized by removing address space corresponding to a memory hole, thereby generating a normalized address. The normalized address is stored in the cache directory. The normalized address is de-normalized, thereby generating a de-normalized address, when the associativity data is cast out of the cache directory to make room for new associativity data. The de-normalized address is sent to the memory system for coherency management.

Abstract: According to one embodiment of the invention, a processor comprises a memory, a plurality of processor cores in communication with the cache memory and a scalability agent unit that operates as an interface between an on-die interconnect and both multiple processor cores and memory.

Abstract: A method of ensuring that data sent to a handheld wireless communications device is written to non-volatile memory is disclosed. In a device, where data is initially written to a first volatile memory and then written to a second volatile memory before being written from the second volatile memory to a non-volatile memory, software code is implemented that causes the writing of the data to non-volatile memory concurrently with the writing of the data to the second volatile memory. The software code may incorporate operating system commands (such as Windows OS).

Abstract: A memory card of one published standard, such as the Multi-Media Card (MMC) or Secure Digital Card (SD), is modified to include the function of a Subscriber Identity Module (SIM) according to another published standard. The controller of the memory card communicates between electrical contacts on the outside of the card and both the memory and the SIM. In one specific form, the memory card has the physical configuration of the current Plug-in SIM card with a few external contacts added to accommodate the memory controller and data memory. In another specific form, the memory card has the physical configuration of the current SD card, including external contacts.

Abstract: Embodiments of the invention exploit the fact that not all portions of a logical volume may include data written by a host. Accordingly, an embodiment of the invention includes setting a designated set of bits to 1 in a meta data table when a logical volume is initialized. These bits may be referred to herein as Never Written by Host (NWBH) bits. Separately, or in combination, an embodiment of the invention includes setting a NWBH bit to 0 when data is written to the associated portion of the logical volume. Separately, or in combination, an embodiment of the invention includes reading the NWBH bit upon receiving a read command associated with the associated portion of the logical volume. If the NWBH bit is equal to 1, data is not read from the associated portion of the logical volume; if the NWBH bit is equal to 0, data is read from the associated portion of the logical volume.

Abstract: It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration such as in creating or deleting a volume or LUN, contents of the alteration are reflected in the database of iSNS or SLP. Also, in response to a change in setting of LUN masking, a discovery domain of iSNS or attribute values of SLP are updated so that the host computer can discover the disk volume. Also, objects and services are reregistered periodically according to a registration period of iSNS or lifetime of SLP to prevent registered contents from expiring.

Abstract: A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.

Abstract: Various embodiments for performing truncate operations in nonvolatile memory are described. In one embodiment, an apparatus may include a nonvolatile memory to perform one or more truncate operations on a data file written to the nonvolatile memory and a volatile memory to track a truncate operation performed in the nonvolatile memory. Other embodiments are described and claimed.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.

Abstract: A computer system including a first storage system connected to a first host computer, a second storage system connected to a second host computer and a third storage system connected to the first and second storage systems. The second storage system sets transfer setting before an occurrence of a failure, the transfer setting being provided with a dedicated storage area to be used for transferring data to the third storage system by asynchronous copy in response to a failure at the first host computer. Before the start of data transfer between the second storage system and third storage system to be executed after an occurrence of the failure, the second storage system checks the dedicated storage area, data transfer line and transfer setting information, and if an abnormal state is detected, this abnormal state is reported to the host computer as information attached to the transfer setting.

Abstract: An apparatus and a method to make data sets conform to data management policies are presented. In one embodiment, the apparatus includes a conformance checker and a conformance engine. The conformance checker may be operable to compare a state of a data set against a data management policy associated with the data set to determine if the data set currently conforms to the data management policy. The conformance engine may then make the data set conform to the data management policy if the conformance checker determines that the data set currently violates the data management policy.

Abstract: The present invention provides techniques, including a method and system, for relocating data between storage systems. In one embodiment of the present invention a host collects usage information from a plurality of storage systems, and determines the relocation destination LU for data stored in the LU to be relocated. The host alters an LU logical position name table that determines matching between the logical position names of data and LUs. It also carries out data relocation between storage subsystems by shifting data stored in an origin LU to be relocated to a destination LU. In another embodiment relocation of files is provided.

Abstract: A system, method, apparatus, and computer-readable medium are provided for expanding the data storage capacity of a virtualized storage system, such as a storage cluster. According to one method, maps are generated and stored that define a stripe pattern for storing data on the storage nodes of a storage cluster. The stripe pattern for each map is defined such that when a storage node is added to a cluster and the data is re-striped according to the new map, only the data that will subsequently reside in the new storage node is moved to the new storage cluster during re-striping. The stripe pattern may be further defined so that during re-striping no movement of data occurs between two storage nodes that existed in the cluster prior to the addition of the new storage node. The stripe pattern may be further defined such that during re-striping an equal amount of data is moved from each of the storage nodes that existed in the cluster prior to the addition of the new storage node to the new storage node.

Abstract: A thin provisioning storage system is able to present a thin provisioned volume to a computer, such that the computer stores data to the volume as if storage space on disk drives was already allocated for the volume. Upon receiving a write request from the computer, in which the write request is directed to an area of the volume for which storage space on the disk drives has not yet been allocated, the storage system allocates new space on the disk drives. When allocating the new space, the storage system obtains a designated performance level for the volume, and determines a number of storage extents to be allocated to the volume based upon the determined performance level. The storage system also is able to take into account performance metrics for the disk drives and/or array groups when selecting locations from which to allocate the storage extents.

Abstract: Described is a technology by which high latency problems with respect to web requests are reduced by having a web proxy server predict and pre-fetch content, in parallel, that is to be requested by a client. The web proxy analyzes a main web page requested by a client to predict subsequent client requests. The web proxy pre-fetches content before the client requests it, by making concurrent requests for the page's embedded objects that exceed the client's limited number of (e.g., two) connections. In one example, the web proxy sends HTTP requests substantially in parallel to a web server, thereby reducing overall latency. In another example, the web proxy server sends parallel requests to a remote web proxy coupled to a web server. The remote web proxy requests only a limited number of objects (e.g., two) at a time, but does so over fast (low latency) connections to the web server.

Abstract: A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information.

Abstract: A plurality of storage devices of a plurality of types is provided. A plurality of criteria is associated for each of the plurality of storage devices, based on characteristics of the plurality of storage devices, wherein the plurality of criteria can be used to determine whether a selected storage device is a compatibility spare for a storage device in a storage device array, and whether the selected storage device is an availability spare for the storage device in the storage device array. A determination is made by a spare management application, based on at least the plurality of criteria and at least one optimality condition, of a first set of storage devices selected from the plurality of storage devices to be allocated to a plurality of storage device arrays, and of a second set of storage devices selected from the plurality of storage devices to be allocated as spares for the plurality of storage device arrays.

Abstract: A design structure for a cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.

Abstract: A method and system for data transfer between a sector-oriented mass storage medium and a host device capable of interfacing with a byte-oriented storage medium using an HS-MMC physical interface in the host device. Existing MMC commands such as FAST_IO command can be used to pass the control data to the sector-oriented mass storage medium and also to read the status of that medium. It is possible to use the GEN_CMD command for data transfer, for example. Because the command in data transfer is similar to ATA protocol, ATA write commands and ATA read commands can also be used for data transfer to and from the sector-oriented mass storage medium.