Abstract: A cache storage system is disclosed which has a high speed buffer (cache), a directory-look-aside-table, and apparatus for maintaining binary coded information signifying the order of use of various sections of the cache. A separately addressable and controllable storage array is provided for each bit position of the binary code so that updating of a code is accomplished by selectively writing certain but not all of the bits in the arrays storing said bits to be updated. This avoids the need to read all bits from an array, change the appropriate bits, then write all bits back into the array. Bits signifying the changed or unchanged state of data in said various sections of the cache are also stored in separately addressable arrays to permit updating of their value merely by selectively writing to the appropriate array.

Abstract: A dynamic address translation mechanism includes a first directory-look-aside-table (DLAT) for 4KB page sizes and a second DLAT for 1MB page sizes. The page size does need not be known prior to DLAT presentation. When a virtual address is presented for translation, it is applied simultaneously to both DLATs for translation by either DLAT if it contains a page address entry corresponding to the virtual address presented. If a DLAT "miss" occurs, segment/page table searching is initiated. The DLAT page sizes are preferably made equal to the segment/page sizes and placed on 4KB and 1MB boundaries. Virtual page addresses lie within either a 1MB page or a 4KB page, and an entry for any virtual address can exist in only one (not both) of the DLATs.