Abstract: A computer system for establishing an adaptive window system within a dynamic model of information systems of organization. The system includes a plurality of editors which enable a user to interact with the system. The window system includes predetermined criteria against which design data of one or more of the editors is compared. An options window then displays those options which meet the criteria, generally corresponding to syntactically permissible options, at any time during the model building process.

Abstract: A computer system for dynamically modeling information systems of organizations by employing partnership sets. The system includes one or more editors which enable a user to interact with the system. The system includes a programmed data computer adapted to establish one or more partnership sets within at least one design data, where each partnership set is representative of zero, one or more partnerships. The computer is further adapted to establish one or more partnerships, wherein each partnership is characterized by one partnership set associated with itself or associated with one other partnership set. The computer controls access to one or more design data by reference to a partnership set which is in partnership with partnership sets of one or more design data.

Abstract: A computer system for processing information representative of complex business transactions. The system enables a user to define business logic within a dynamic information management system model. The system may include a plurality of editors which enable a user to dynamically create, analyze and modify design data. The system further includes graphical displays which enable a user to affect the operations to be performed on that design data.

Abstract: A method and apparatus is disclosed for control of a central processor in response to a branch instruction using two separate, subsequently updated condition codes. Computer architecture is provided wherein the condition codes which determine the processor state result from the execution of instructions prior to the currently executing instruction. When the preceding instructions are executed, condition codes are set and maintained in a first condition code register. The first condition code is transferred to the second condition code register, and the first condition code register is updated to reflect the result of the current instruction execution. Any condition code state such as a branch used by the third instruction is based on the condition code state maintained in the second condition code register.

Abstract: A bus programmable slave module card 30 for use in a computer control system which comprises a master computer and one or more slave computer modules interfacing therewith by means of a bus and wherein each slave module includes its own microprocessor memory, and control program for acting as a single loop controller. The slave card includes a plurality of memory means corresponding to a like plurality of memory devices in the master computer, for each slave memory means its own communication lines connectable through the bus with memory communication lines of an associated memory device in the master computer, and a one-way electronic door which is switchable to either a closed condition or a one-way open condition. With the door closed, communication lines between master computer memory and slave memory are blocked.

Abstract: A signal processor comprising a split pipelined parallel processor which processes data signals from external signal sources and provides signal processing functions utilizing a plurality of data formats. The signal processor comprises an external interface unit having a serial control port and a plurality of bidirectional parallel ports. The interface unit transfers control and data signals between the signal processor and external devices. The parallel ports are configurable as individual parallel ports or coupled pairs which form a port having the combined data path of the two coupled ports. An arithmetic element controller comprising a microprogram memory and a control program memory is coupled to the interface unit which loads applications programs into the control program memory and executes the programs. The arithmetic element controller controls the processing of control and data signals in the signal processor.

Abstract: A block MOVE instruction allows a programmer to issue an instruction to a loosely coupled system bus controller, thereby facilitating the execution of a memory to memory move of multiple data entries, utilizing a burst mode transfer onto the system bus for both reads and writes. The instruction allows the programmer to fully utilize the maximum bus bandwidth of the system bus for memory to memory transfers of data (e.g. DMA, block moves, memory page initialization) and transfers of instructions/data to detached coprocessors.

Abstract: A data processing system includes cache memories for storing instructions and operands. An execution unit stores instructions in an instruction FIFO, operands in a data FIFO and offsets in an offset FIFO. Offsets indicate the location of operands relative to a memory word boundary. Instructions read from the instruction FIFO are applied to a control store subsystem which reads out a firmware word. Specified firmware bits condition multiplexers in the data path to align the operands on the fly during the execution of the instruction.

Abstract: This invention relates to a method of establishing a staple relationship between two documents within a context of a folder document stored in an informtion processing system. An end user indicates to the system that a staple relationship is to be established between two identified documents. The end user enters a definition of the staple relationship which includes any attributes to be associated with the identified documents within the staple relationship and at least one folder document within whose context the relationship exist. The system will create the staple relationship and file the identified documents in a library within the context of the specified folder document. The system then maintains the staple relationship between the identified documents within the context of the specified folder document.

Abstract: A computer system for processing complex information representative of business transactions. Specifically, the system stores transaction data, which is then reversibly transformed in accordance with predetermined processing algorithms, while it is externally inaccessible. In this static state, the transformed transaction data is evaluated against predetermined logical criteria. The evaluation produces either successful or unsuccessful results. If successful, the transformed data is then made externally accessible. If unsuccessful, the original transaction data is made externally accessible.

Abstract: A computer-aided design method for restructuring computational networks to minimize latency and shim delay, suitable for use by a silicon compiler. Data-flow graphs for computational networks which use trees of operators, each performing associative and commutative combining of its respective imput operands to generate a respective output operand, are converted to data-flow graphs with multiple-input operators. Data-flow graphs with multiple-input operators, after being optimally scheduled, are converted to data-flow graphs which use trees of dual-input operators or of dual-input and three-input operators, those trees having minimum latency and shim delay associated with them. These data-flow graphs then have shim delay minimized in them, e.g. by being subjected to linear programming.

Abstract: A method and apparatus for sorting object data, the object data having a data format of a next address and a record. The next address indicates the address of another object data, and the record includes information data which is the subject of the sort. The sorting method and apparatus perform two sorting processes. The first process performs a divisional sort which sorts the object data into blocks of object data; these blocks being sorted with respect to one another. In sorting the object data into these object data blocks, it is unnecessary to actually move the object data within the memory. Instead, only one address of an object data out of all the object data in a block needs to be stored. Use is made of the next address of the object data to link the remaining object data to the single object data stored in an object data block. Then the second sorting process performs a sort of the object data in each block; thus all the object data becomes sorted.

Abstract: A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor, and also provides a watchdog function to monitor the microprocessor's activity. The auxiliary chip itself can put to sleep by the microprocessor to minimize power consumption. The sleep mode of the auxiliary chip saves power by shutting down many of the input-sensing circuits, and the watchdog function. The sleep command is not accepted unless it stands in the proper timing relationship to a signal on the strobe pin. This permits the power savings of the sleep mode to be realized, without any risk of the system being placed in the sleep mode due to an out-of-control system condition.

Abstract: A parallel processor developing system comprises a control computer, an interface portion, a processing element, a tracer portion and a display portion. The processing element comprises a data driven type processor. The interface portion stores data packets supplied from the control computer and applies the data packets to the processing element at a predetermined time interval. The tracer portion stores the data packets supplied from predetermined ports of the processing element together with time information. The display portion displays storage contents of the tracer portion.

Abstract: Control of communication by a plurality of devices, such as computer programs and terminals, via a computer is controlled by an arrangement referred to as a connector. The connector receives a request for communication defining the devices to the communication and, in response to the request, establishes a mapping table defining the source devices and destination devices to the connection. A source device stores data in connector memory and the connector reads the mapping table to determine the destination devices for the stored data. The connector then creates a linked list coupling structure between the stored data and the determined destination devices. The destination devices issue read commands to which the connector responds by reading the stored data in accordance with the coupling structure and providing that data to the requesting device.

Abstract: A last-in, first-out register having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the addresses already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be retransferred to the buffer address register for read out.

Abstract: A computer program permits a user to simulate configuring add-in boards for a computer system. A board may be "pulled" from an inventory list for inspection, and may be "inserted" into any legal slot in the computer system. The program can automatically generate any permissible configurations for the board, i.e., configuration of the board's address resource allocations that avoid conflicts with the address resource allocations of other, already-installed boards. The user may select from among permissible configurations; for a selected configuration, the user may display to screen or printer a drawing of the switch- and jumper settings on the board that are needed to implement the selected configuration.

Abstract: A data processor is provided with a mechanism for controlling its performance. The processor is allowed to run normally for R clock beats, and then further instruction starts are inhibited for W clock beats. The ratio W/R determines the level of performance of the processor.

Abstract: An image processing controller comprising a pulse control signal generator for controlling a load. A memory is provided for storing parameters, such as the period and duty factor of the pulse control signal. The parameters are transferred from the memory to the pulse control signal generator. The pulse control signal generator generates a pulse control signal having a predetermined pulse width at a predetermined period, in accordance with the parameters.

Abstract: A computer system for dynamically modeling information systems of organizations. The system includes a plurality of editors which enable a user to interact with the system. Included in the system is an information modeler, an information flow modeler, and a logic modeler for creating, analyzing and modifying design data associated with each modeler. Each of the modelers are dynamically interlinked, such that a change to one design data set will affect a corresponding change in other design data sets. The system includes graphic representations associated with each of the modelers to enable a user to interact with the system. The objects of each of the graphic representations may also be dynamically linked, such that a change in one representation affects a substantially immediate change in other representations.