Abstract: An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

Abstract: A computer system which flushes the cache controller when a circuit board is being configured or is responding to an input/output write operation. The flush operation can be disabled for each circuit board location. A cache flush operation can also be directly requested.

Abstract: A linear data set is mapped to one or more non-main storage virtual data spaces. Portions of this data space are then selectively mapped to a "window" in an address space in which an application is executing, and changes made in this "window" are temporarily saved in the data space. After completion of processing, the application may permanently save changed data from the data space to the linear data set.The technique for mapping the data space to the address space may be used to map between two address spaces, and may be extended to encompass third and subsequent spaces, so that a reference to a mapped address in the first space will ultimately be interpreted as a reference to an address in the last mapped space.

Abstract: In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address.

Abstract: A method performed within a multi-processing, multi-programming computer environment for reducing conflict among tasks concurrently accessing COMMON BLOCKs in code sequences compiled within said environment from a FORTRAN like language system, and for reducing the memory used in the storing of private copies of said COMMON BLOCKs. The method involves inserting constructs at compile time into the compiled code which enable the COMMON BLOCKs to be dynamically bound at runtime to two or more referencing tasks. Then, at execution time responsive to the constructs, the blocks are bound to the tasks dynamically and scoped so that they lie within the dynamic nesting of the tasks.

Abstract: An industrial controller monitors its state as comprised of selected inputs and outputs for a present time period and a previous time period. Each current state is compared to a previously acquired list of stored states to detect possible errors in inputs to the industrial controller and to find the closest match of the current state to a previously stored state. This "closest match word" is used to identify erroneous inputs to the industrial controller and to determine whether the controlled process must be halted. The closest match word may be substituted for the current state to permit the controlled process to continue.

Abstract: A method for allowing weak-searchers of a B+-tree avoid locks that serialize access to the B+-tree structure. The update technique used to achieve this ensures that the B+-tree is always in a correct state on secondary storage so that repair is not necessary after a system failure. The assumption is made that the readers will complete their reading within a specified period but sometimes will need to be restarted because they have not completed their reading within a predetermined time period.

Abstract: A real-time, concurrent garbage collection system and method uses the virtual-memory page protection mechanisms of a standard computer system to collect used storage space in a heap. The heap is divided into old-space and new-space portions, each of which is further divided into a multiplicity of pages. At least one mutator thread modifies and adds objects to new-space. Two garbage collection process threads are used: a fault processing thread, and a concurrent scanning thread, both of which help to collect the accessible objects in old-space. The garbage collector initially copies only the root objects, or a portion of the root objects, to new-space. In addition, all pages of new-space which contain copies of old-space objects are initially marked as being protected. Whenever the mutator tries to access an object in a protected page, a page-access trap is generated.

Abstract: In the conventional branch address calculator for an advance control processor, when a branch instruction reaches the execution step, a decision is first made as to whether the branch instruction is conditional or non-conditional, and then a target branch address (logical address) is calculated before the branch instruction is executed, so that the processing speed is slow. To increase the processing speed, a target branch address is previously calculated before a branch instruction reaches the execution step. Since the branch instruction can be executed immediately after the condition of the branch instruction has been decided, it is possible to eliminate the time required to calculate the target branch address after the instruction has reached the execution step.

Abstract: A method of translating a sentence including an adverb phrase put between two commas by using a translating apparatus which includes a dictionary look up and morpheme analyzer for looking up each word constituting an input sentence of a source language in a dictionary and providing a morpheme array of the input sentence from information obtained by looking up the dictionary, syntax analyzer for analyzing a syntactic structure of the morpheme array provided by the dictionary look up and morpheme analyzer with dictionary and grammatical rules, a converter for converting the syntactic structure analyzed by the syntax analyzer into a corresponding syntactic structure of a target language, and a generator for generating a translation in accordance with the syntactic structure of the target language received from the converter referring to the information obtained by looking up the dictionary, in which the adverb phrase is translated firstly, and then the input sentence is translated after the adverb phrase is remo

Abstract: A method of evaluating and predicting the performance of an I/O disk system comprised of one or more disk controllers and cooperating disk units using a simulation model containing a stact constructed such that delays are formulated as sets of stochastic processes. The simulation model includes at least one statistical submodel and has delay parameters which are settable in accordance with a selectable I/O disk configuration. The simulation model is driven by a selectable I/O workload snapshot grouped into I/O batches. The simulation model provides both overall and batch output data in response to the I/O workload snapshot. Provision is also made for the simulation model to take into account the presence of cache storage in the selected I/O configuration.

Abstract: In a network system comprising a plurality of secondary LAN's of different types operable at a relatively low speed, a single primary LAN accommodating the secondary LAN's and operable at a relatively high speed, and a plurality of bridges for connecting the primary LAN and the secondary LAN's, a communication frame transmitting on the primary LAN includes an identifier representative of the type of a secondary LAN to which a source terminal belongs and a bridge receiving the primary LAN frame carries out a protocol processing on the basis of the identifier representative of the type of the secondary LAN.

Abstract: A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division multiplexed with data bits when both are written to external circuitry. In a second or normal mode, the circuit's address and data terminals are not connected and address bits are communicated with the circuit independent of data bits which are communicated with the circuit. No circuitry external to the integrated circuit is required to implement the multiplexed mode. A control portion insures that bit collisions are avoided when the circuit is in the multiplexed mode.

Abstract: A controller such as a CRT controller is connected to a microprocessor via a system bus and has connecting terminals for its peripheral units. This controller is provided with a control terminal for receiving the control signal supplied from the microprocessor and control means for providing high impedance at the connecting terminal in response to the control signal. The controller having such a construction permits the microprocessor to directly access the peripheral units.

Abstract: A virtual machine system for executing fast speed address translation in plural virtual machines having a two-stage address translation mechanism. The system permits address translation to be executed by adding to an output from a first address translation address constants in a hold apparatus holding address constants including zero, executing a second address translation, and selecting an output from the first address translation to which the address constants have been added or an output from the second address translation. An address translation for a plurality of different regions is performed by switching a value for the address constants held by the hold apparatus.

Abstract: A printer controlled by a CPU in which a ROM having stored therein a control program executed by the CPU in replaceable. The ROM has stored therein identifying codes for identifying the control program stored in the ROM, and initializing data. A nonvolatile memory capable of being read out and written and having contents retained even if a power switch is turned off is provided with memory areas which can store respectively the identifying codes and the initializing data stored in the ROM in an identical array fashion. Each time the power switch is turned on, the identifying codes stored in the ROM are compared with identifying codes stored in the nonvolatile memory. If the identifying codes in the ROM and the identifying codes in the nonvolatile memory are inconsistent with each other, the identifying codes and the initializing data stored in the ROM are transferred and written respectively to the memory areas of the nonvolatile memory.

Abstract: A method and apparatus are disclosed for dynamically promoting a selected background window displayed on a computer system among a plurality of windows which at least partially overlap the background window. The output of data from the selected background window is monitored and is utilized to selectively provide an unencumbered display by altering the display sequence of the windows to automatically promote the background window to the uppermost display position, in accordance with the state of a display attribute associated with the background window. After the output of data by the selected window has occurred, the display attribute may be utilized to determine whether or not the selected window returns to its previous display position or remains in the uppermost display position.

Abstract: A method of setting the operating parameters in a microprocessor controlled typewriter or like office machine having a microprocessor, a set-up initiating actuator, a data input keyboard which includes (i) a printer-advance actuator, (ii) a first command actuator, and (iii) a second command actuator, a memory, a record carrier, and a printing apparatus including the steps of:(a) actuating the set-up initiating actuator disposed on the keyboard to enter a set-up mode and to recall a set-up plane which lists a plurality of sub-planes;(b) displaying the set-up plane on the record carrier;(c) selecting one of the plurality of sub-planes by using the printer-advance actuator;(d) actuating the first command actuator to recall from memory the selected sub-plane and to print the parameters of the selected sub-plane upon the record carrier;(e) selecting one of the values of the selected sub-plane by using the printer-advance actuator;(f) storing the selected value in the memory;(g) actuating the second command actuato

Abstract: A programmable logic controller is provided which includes a function block processor for processing function block instructions and a bit processor for processing Boolean instructions. The bit processor decodes and identifies the OPCODE of each instruction command in a user program memory and returns control to the function block processor if at least one of the following two conditions occurs, namely, 1) there is power flow in the power flow register of the bit processor and 2) the function block is one which must be executed by the function block processor. The bit processor waits until the function block processor has retrieved the instruction pointer from the bit processor and then adjusts the instruction pointer to point to the next OPCODE in the user program memory.

Abstract: The desk-top calculator in accordance with the present invention comprises a constant access key, a ROM and a control unit. The ROM is arranged such that different types of constants are anteriorly stored therein and the constants are accessed through the operation of the constant access key. The control unit is arranged such that, as well as accessing successively the different types of constants stored in the ROM each time the constant access key is operated consecutively, after one of the contants is accessed through the operation of the constant access key, when another key is operated and the constant access key operated again thereafter, the control unit accesses the constant previously accessed in the first place.According to the arrangement described above, the operation of such a desk-top calculator is simplified and its operation efficiency is sharply improved.