Abstract: An image filing system in which additional document identification data is used in addition to main document identification data for the identification of an image-bearing document and is formulated typically on the basis of a predetermined relationship detected between the number of times which a given document has been searched for and the number of times which the document has been used for printing purposes so that the main document identification data assigned to the document and used for the searching of the document is deemed inappropriate depending on the resultant count numbers for displaying and printing whereupon a message to that effect is issued to prompt the operator of the system to change the keyword.

Abstract: A programmable element sequence selection circuit which selects a repeatable sequence of elements from a plurality of elements is provided. The sequence selection circuit includes a sequence storage circuit into which a sequence of element identifiers is loaded and accessed.

Abstract: A pipeline circuit is capable of adjusting the timing of data, in a data processing system for ensuring processing, even if the input timings of different data are irregular or the input data are invalid. This is achieved by generating a selection signal, which is input to a data holding circuit. The selection signal determines the particular register in which a datum is stored. The value of the selection signal is determined by an input indicating signal, which indicates whether a particular datum is valid or invalid. When the data is valid the selection signal is shifted to the next value, indicating the next higher register, and when the data is invalid the selection signal maintains the value it had for the previous datum.

Abstract: A multiprocessor computing system having a plurality of processors 11-23 and a plurality of switches 31-43 is interconnected such that a single one of said switches 31-43 is between any pair of said processors 11-23.

Abstract: In a data processing unit having an instruction precontrol function, when an instruction for new address mode setting, branch address generation and branching is decoded in a preexecution cycle of the instruction, a branch destination address is calculated by using an address mode of the branch destination address represented by a specific bit in operand data of the instruction, as the address mode, and the branch destination instruction is fetched based on the calculated address.

Abstract: A distributed digital data processing system includes a plurality of nodes which communicate over a network. A node maintains one or more objects, each of which may be a file, that is, an addressable unit in the system, such as a program, database, text file, or the like, or a directory which may contain one or more files or other directories. One node maintains a naming service which associates each object in the system with one or more protocol towers. Each protocol tower identifies the object name and a series of entries each identifying a name for each of the protocol layers, along with the communications parameters and address information, to be used in communicating with the object. When a node requires access to an object maintained by another node, it first retrieves from the naming service the protocol towers for the object. The node also maintains a tower identifying the names of each of the protocols over which it can communicate.

Abstract: In a first-in-first-out register device positioned intermediately between an address calculation circuit and an operation execution circuit, both of which are individually operable in pipeline fashions, a stage number is varied from one to another in a register unit having a plurality of register stages, in consideration of an execution time which is necessary for a bus access operation carried out in response to a read instruction and which is variable. A maximum usable stage number is determined by a pointer control circuit in response to the variable execution time and is compared with an actual stage number, which is sent from a detector and which indicates an actual stage of the register unit. As a result, the register unit is controlled, so that the actual stage does not exceed the maximum usable stage.

Abstract: A method of monitoring objects in an interactive object-oriented database system. Any of a plurality of client programs can request monitoring of attributes of objects in the database. A record is kept of update transactions initiated by a client. When the client commits the changes, any client which has requested monitoring is notified of any change in the value of an attribute being monitored at the request of that client. The notification interrupts the client and invokes a predesignated client procedure. Overhead is minimized by creating partial view materialization paths and defining monitors ahead of time and by localizing the monitoring.

Abstract: A method of initiating a write operation for a particular command from a first computer module through a system interface to a second computer module having data registers, and a status register which includes the steps of writing data to the data registers in the second computer module, and determining the status of the status register in the second computer module to cause the initiation of the particular command by which the reading the status of the data registers and issuing the particular command as separate steps are eliminated.

Abstract: A synchronization circuit synchronizes asynchronous parallel byte words input data with synchronous parallel byte output data so as not to glitch or interrupt required regular flow of synchronous data to end user devices.

Abstract: In a data processing system in which each of the data processing units is implemented using pipeline techniques and has a cache memory unit employing a store through strategy, the time required to prepare a write instruction operand address can be substantially shorter than the time required by the execution unit to prepare the associated write instruction operand. In order to utilize the time difference, apparatus is included in the execution cache unit for storing the write instruction operand address during the preparation of the associated write instruction operand. After storing the write instruction operand address, a next address is entered in an input register of the execution cache unit. When the newly entered address is associated with a read instruction, does not conflict with the write instruction operand address, and produces a "hit" signal when applied to the execution cache unit tag directory, the read instruction is processed by the execution unit.

Abstract: In a multiprocessor system comprising a primary processor and at least one subsidiary processor, the primary processor carries out an operation by the use of a predetermined address space divided into first and partial address spaces assigned to the primary processor and to both the primary and the subsidiary processors in common, respectively. The primary processor is coupled to a primary local memory defining the first partial address space while each subsidiary processor is coupled to a common memory to which the second partial address space is assigned by dividing the second partial address space. Each common memory is coupled to the primary processor through a first gate circuit and to each subsidiary processor through a second gate circuit. The first and the second gate circuits are controlled by a controlled to selectively connect the primary and each subsidiary processors to the common memory and to thereby share the same with the primary and each subsidiary processors.

Abstract: A method for performing inter-processor communications in a multiprocessor system combines the sending of a message with the sending of a message interrupt. Messages are exchanged through a shared memory organized into pages, each of which may be "owned" by a processor. When a sending processor executes a store instruction that stores its operand to a memory area owned by a destination processor, a message interrupt is presented to the destination processor. If the destination processor is interrupt enabled, the operand of the store instruction is stored at the address specified by the store instruction and that address is stored in a register of the destination processor. Execution of the store instruction by the sending processor then completes.

Abstract: A vector processor is closely integrated with a scalar processor. The scalar processor provides virtual-to-physical memory translation for both scalar and vector operations. In vector operations, a block move operation preformed by the scalar processor is intercepted, the write command in the operation is converted to a read, and data resulting from a vector operation is returned to the address specified by the block move write command. Writing of the data may be masked by a prior vector operation. Prefetch queues and write queues are provided between main memory and the vector processor. A microinstruction interface is supported for the vector processor.

Abstract: A jump prediction circuit predicts the outcome of a conditional jump instruction and is of particular use in a pipelined processor. An initial guess is formed, based on the value of the jump parameter in the instruction. A random-access memory stores the history of the outcome of previously executed jump instructions and is used, when valid, to correct the initial guess to produce a final jump prediction.

Abstract: A method and apparatus are disclosed for monitoring software applications within a first processor during development thereof. A limited number of uniquely identifiable elements or "hooks" are inserted into the software application under development and each time an element is encountered during processing of that software application, the identity of the element and a selected data frame are coupled to the output bus of the first processor. A data output card is utilized to couple that information to a data collection card via a dedicated cable. The data collection card is then utilized to transfer the identity of each element encountered and its associated data frame along with a time value, to a second processor, which is utilized to record that data. In one embodiment of the present invention, a switched bank memory system is utilized in the second processor to permit high speed data storage.

Abstract: A direct memory access controller coupled to a system bus for controlling a data transfer by a direct memory access comprises an internal bus, a data handler coupled to the system data bus and the internal bus for controlling an exchange of data between the system bus and the internal bus, a microsequencer which controls by microprograms parts of the direct memory access controller in units of one system clock cycle during one present transfer cycle, and a programmable logic array part supplied with a transfer request, a transfer mode information and at least portions of a transfer address and a byte count. The programmable logic array part is coupled to the internal bus and outputs control information required during a next transfer cycle during one transfer cycle which corresponds to a predetermined number of system clock cycles.

Abstract: A reconfigurable counter is provided which includes first and second memories coupled via a common bus to a microprocessor which controls the process of configuring and reconfiguring the counter. A programmable hardware array, coupled to the microprocessor, is capable of being programmed to emulate a plurality of different counter types. The first memory stores a plurality of different counter configuration profiles, each of which corresponds to a different type counter configuraiton. In one or more of the selected counter types, different counter modes such as an up-down counter mode, pulse direction counter mode and A quad B counter modes are available.

Abstract: Apparatus for delivering and receiving mail using a computer system with a mail directory file thereon. Each mail directory file in the mail delivery system having a user entry for mail recipients. The apparatus having a directory extract and update capability so that user directory entries may be changed on different mail computer systems.

Abstract: A peripheral device controller has an EEPROM which stores microinstructions to be placed in a random access memory control store. The EEPROM also stores peripheral configuration information. This information is obtained by polling the peripheral devices connected to the controller and storing the resulting information in the EEPROM. Upon powering up, the microinstructions stored in the EEPROM are transferred to the control store via execution of instructions held in a boot PROM. The controller, therefore, provides a fast control store while maintaining permanence of the microinstructions after power is extinguished. Means are also provided to update the control store and EEPROM. The EEPROM may upon CPU command be updated with new microinstructions held in main memory or obtained from peripheral devices.