Abstract: A subchannel memory access control system for use in a data processing system having multiplexor channels to which input/output control units of a first group are connected, and block multiplexor channels to which input/output control units of second and third groups are connected. A plurality of input/output devices of corresponding groups are connected to each control unit.

Abstract: A data handling apparatus of solid state construction for a data processing system. The apparatus has a storage and input/output gates for peripheral units. The storage includes input and output counters for generating storage addresses which, respectively, determine a location for useful data to be temporarily stored while in transit and a location to which such data is to be emitted. The counting modes can be switched to accomodate connecting two or more units of the data processing system. A comparator is connected to the counter outputs and produces therefrom an indication of the state of occupation of the various storage locations.

Abstract: A micro-computer system includes a memory device, a plurality of memory utilization devices such as processors, a bus connected between the memory device and the memory utilization devices for address information and data transfer therebetween, bus control lines, and an access arbitrator for preventing simultaneous accesses of memory utilization devices to the memory device. The bus control lines include two lines for transferring address transfer and write/read control information from one of the memory utilization devices to the memory device and one line for coupling an access acknowledge signal from the memory device to one of the memory utilization devices. The access arbitrator couples the access acknowledge signal to one of the memory utilization devices issuing an access request signal and disables another memory utilization device to issue the address transfer and read/write control information on the two bus control lines.

Abstract: A common electrical bus for coupling a plurality of units in a data processing system for the transfer of information therebetween. The units are coupled in a priority arrangement which is distributed thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchronous manner. Each of the units includes priority logic which includes logic elements for requesting a bus cycle, such request being granted if no other higher priority unit has also requested a bus cycle. The request for and an indication of the grant of the bus cycle are stored in each unit so requesting and being granted the bus cycle respectively, only one such unit being capable of having the grant of a bus cycle at any given time, whereas any number of such units may have its request pending at any particular time.

Abstract: A modular digital signal processor based on a master-slave architecture has the capability of expanding its processing power by aggregating additional modules in a tree type structure. In such a processor the control functions are subdivided into groups, each for performance in a distinct control unit. One or more of the control units can perform a master function with respect to one or several slaved control units and can itself be a slave to a higher level control unit. The arithmetic data functions of the processor are performed in pipe line multiplier-accumulator units (PMAU), each of which is controlled by, instructions from an associated control unit.

Abstract: A system for resolving conflicts among processors for access to a memory to which the processors are connected by a first bus includes a number of logic circuits, one for each processor. Each logic circuit receives a number of inputs to determine when access to the memory can be had for its processor. These inputs include a memory use request made by the processor, a memory availability signal communicated to all the logic circuits over a second bus, and the longest available processor waiting time, communicated to all the logic circuits over a third bus.

Abstract: A memory control structure for a pipe-lined mini-processor which allows the processor to work with relatively slow memories without degradation of performance. The memory structure includes a memory selector which provides an interface between the processor output and the inputs of a plurality of memories of different types and speeds. The memory selector receives address and control information from the processor and generates the timing and selection signals for the memories. The memory structure also includes fan-in circuitry connected to the outputs of all the memories. The fan-in circuitry includes latches for sampling the output of each memory and multiplexing the memory outputs onto a single data bus for transfer of data from the memories to the processor.

Abstract: A cursor circuit for an on-the-fly digital television display system. The host digital television display system employs an intermediate buffer which stores a coded representation of the symbol only during the period of its display. In order to obtain access of the encoded symbol in storage with a conventional light pen, the circuit secures the identity of the encoded symbol in the intermediate buffer during the first display frame. This identity is the address of the symbol as stored in a refresh buffer. This identity is made available for accessing the refresh buffer during a second display frame. This enables convenient access of the encoded symbol in an on-the-fly digital television display.

Abstract: A minicomputer system comprising an arithmetic control unit integrated on a one-chip semiconductor device using n-channel silicon gate E/D MOS technology and a control storage separate from and connected to the arithmetic control unit for storing microinstructions. The arithmetic control unit includes two kinds of read only memories, each having a small memory capacity. The first read only memory stores start addresses of specific microinstructions for phase control, an illegal instruction trap and an initialization trap. The second read only memory stores auxiliary microinstructions to handle operations involving an accumulator, general registers and an instruction register in the arithmetic control unit.

Abstract: A machine for emulating the results of multi-level storage hierarchies by providing an associative storage directory for each level other than main storage. Address sequences to drive the directories are derived from a single level digital computer by recording sequences on tape or by dynamically monitoring computer operation. Individual addresses are skewed an appropriate number of bits depending upon the block size and the number of classes being emulated at any given level, so that those bits of the monitored address indicating segment name are presented to the directory for comparison with its contents in the appropriate class. Means are provided for transposing the segment and class names at higher levels to segment and class names at lower levels. Counting means are provided to record hits, misses and pushes at various levels in order to provide data for calculating average access times for the particular multi-level storage hierarchy being emulated.

Abstract: A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.

Abstract: A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device.

Abstract: An arithmetic processor includes an input buffer and a result buffer connected through a pair of multiplexers to a pair of working registers feeding three parallel execution units. Operands stored in the buffers are selected for processing by addressing the buffers and multiplexers. Instruction overlapping is provided whereby operands of one instruction are read in parallel with the execution of the previous instruction. Further, reverse operations are processed identically as forward or normal operations except for addressing thereby achieving invarience of performance under non-communicative instructions.

Abstract: Graphical information, such as a structural chemical formulae, composed of nodes and links between the nodes, or in a chemical formula ring positions and bonds, are coded by means of logic circuits responsive to actuation of a keyboard. The graphical data coded in binary digit form are stored, while contents of the store are scanned, decoded and applied in analog form to a display device. When recorded on a suitable medium they are made machine readable, for searching or similar processing. A luminous cursor indicates on the display the part of a structural formula that is subject to the next keyboard action. The store is organized about fixed display locations available as nodes. Alphanumeric characters identify atoms at nodes. Single, double or triple bonds in any of eight directions from a node towards another node may be registered and displayed. A cursor address register, a store address register and a comparator are used.

Abstract: A system and method for providing a control store arrangement in which a single memory having a plurality of memory locations can be used for storing sequences of microinstructions or scratch pad information. The number of storage locations defining the scratch pad area can be increased or decreased as required by assigning tag addresses to a desired number of scratch pad storage locations when the microinstruction routines are being assembled. In this manner, the locations defining the scratch pad areas can be tailored to the particular system operation to be performed. This eliminates the need for modifying the control store circuits to change the size of the control store scratch pad area.

Abstract: An associative system for providing virtual paged stores with on-chip associative address translation and control functions. Each of a plurality of integrated circuit chips contains the storage cells for a unit of data and at least one associative circuit including a virtual page address register for storing the virtual address bits assigned to each page. The CPU includes a virtual page address register and a real address register, with the CPU virtual page address register being connected to the virtual address register on each chip for interrogating the chips when a page request is made. The real address register holds the real address bits for selecting a byte of data from the chips. An interrogate virtual page address is applied to each of the chips for comparison with the address stored in the virtual page address registers, whereby a match will directly enable the selected chip to be read and/or written into.

Abstract: A digital monitor for monitoring the operation of a synchronous digital system. Proper operation of the monitored digital system is determined by storing a predetermined sequence of digital numbers in a memory. The bit patterns generated by the system being monitored are utilized as addresses to read the stored digital numbers. After each read cycle the digital number read from the memory is examined to determine if it has the proper value. If the value is not proper, a memory is set indicating that the system being monitored has malfunctioned. Additionally, the number of bit patterns checked during each cycle of the system is determined. If the correct number of patterns are not checked, the memory is also set indicating that a malfunction has occurred. Apparatus for monitoring a selected number of analog signals such as power supply voltages is also provided. Either of these tests may be inhibited by signals from the system being monitored or by signals from an external source.

Abstract: A visual display for an electronic accounting computer comprising a keyboard and a console. The computer concurrently executes two programs. The console is provided with a changeover switch for selectively allocating the keyboard, the display and the console to one of the programs. As introduction from the keyboard is required, an operator guidance message is displayed. This message is replaced by the response of the operator when it is initiated. If the program not selected by the allocating switch requires attention, an operator call message is developed. The changeover switch is moved to select the program requiring attention. An appropriate message requesting the needed data is displayed, to be replaced by the data as the operator introduces it. The operator then repositions the allocating switch, and the message defining the next required introduction of the original program is displayed, so that data introduction may resume.

Abstract: A system for monitoring the logic conditions at the external addressable locations of a programmable controller wherein intermediate memory units are provided for controlling separate input and output locations. The controller periodically sequences the data in the intermediate memory units to maintain the logic conditions in the input and output locations. If the logic conditions are to be updated, the controller obtains access to the sequencing arrangement and changes the logic conditions within the intermediate memory units. Thereafter, the sequencing continues to maintain the desired logic conditions in the input and output locations.

Abstract: Interface circuitry for effectuating the control of a printing unit that employs a cursor moving in a scanning raster to effect permanent recordation on a laminar print media, such as paper. The interface circuitry includes a buffer storage unit for receiving high speed digitized signals designating characters to be printed. Corresponding video signals are accessed within the interface circuitry and are provided to the printer. The circuit elements and timing devices define a two dimensional matrix of area locations of uniform geometry. Video signals controlling the print characteristics in a row of area locations are accessed out of memory in the interface circuitry and are serially relayed to the cursor to produce a pattern of light and dark areas in a row within the field within which the character is to be printed. Provision of video signals in this manner is repeated until the video signals have been provided for all character positions through which that row passes.