Abstract: A low capacitance n-channel analog switch circuit, a p-channel analog switch circuit, and a full CMOS transmission gate (T-gate) circuit are described. Resistive decoupling can be used to isolate the switch or T-gate from AC grounds, such as one or more switch control signal inputs or supply voltages. A semiconductor region that is separated from a body region of a pass field-effect transistor (FET) can be coupled to or driven to a voltage similar to the input voltage or other desired voltage to help reduce parasitic capacitance of the switch or T-gate. The switch or T-gate can have improved frequency bandwidth or frequency response. The switch can be useful in a programmable gain amplifier (PGA) or programmable gain instrumentation amplifier (PGIA) or other circuit in which excessive switch capacitance could degrade circuit performance.

Abstract: A clock correction device performs skew adjustment and duty correction of an input clock concurrently or in parallel. The clock correction device includes a correction circuit that performs skew adjustment of an input clock by analog control using a skew adjustment signal based on a phase difference between an output clock and a reference clock, receives a duty control signal, and performs duty correction of the input clock by digital control, a skew detection circuit that receives inputs of the output clock and the reference clock and, when only the reference clock is in a predetermined state, outputs a detection signal that changes to the predetermined state, an integration circuit that integrates the detection signal and generates a first voltage signal, and a comparator that compares the first voltage signal and a first reference signal to thereby generate the skew adjustment signal.

Abstract: An apparatus includes a first AC (alternating current) coupling circuit configured to receive a first end of a differential signal and output a first coupled signal in accordance with a bias voltage; a second AC coupling circuit configured to receive a second end of the differential signal and output a second coupled signal in accordance with the bias voltage; a first complementary joint-control cascode pair configured to shunt the first end of the differential signal to a DC (direct current) node in accordance with a joint control by the first coupled signal and the second coupled signal; and a second complementary joint-control cascode pair configured to shunt the second end of the differential signal to the DC node in accordance with a joint control by the first coupled signal and the second coupled signal. A related method is also provided.

Abstract: A method of compensating for integral nonlinear interpolation (INL) distortion in a clock synthesizer driven by a system clock running at a frequency fsys, involves introducing a selected nominal analog delay I*dt with an actual delay of I*dt+? at the output of the a first path with a digital controlled oscillator (DCO) and a digital-to-time converter (DTC) and a nominal digital delay I*D with an actual delay of I*D+? at the input of a second path with a DCO and a DTC that offsets the actual analog delay in the first path, adjusting the contents x(k) of a compensation module in the second path to align the output pulses of the first and second paths for different values of k, where k represents an interpolation point, iteratively repeating the two preceding steps for all N values of I, and averaging the contents x(k) of the compensation module to derive the compensation values to be applied to a one of the DTCs to correct for INL distortion.

Abstract: In a step-up circuit, which is an electronic control device, changes in current caused by a current rise when stepping up is started and a current drop when stepping up is stopped generate magnetic induction noise due to fluctuations in the electromagnetic induction voltage in signal lines around the step-up circuit. The present invention is a step-up circuit for stepping up by current control, wherein the step-up circuit is provided with a plurality of target current values for retaining a step-up current so that the current is raised in a stepwise manner when stepping up is started and dropped in a stepwise manner when stepping up is stopped. The present invention reduces electromagnetic induction noise generated by the changes in current when stepping up is started and when stepping up is stopped.

Abstract: A primary circuit outputs, in response to an input signal, a first signal with a first reference potential. A level shift main circuit converts the reference potential of the first signal received from the primary circuit to a second reference potential to output a second signal with the second reference potential. A secondary circuit generates an output signal with the second reference potential using the second signal. At least one rectifying element circuit is provided between the primary circuit and the secondary circuit. At least one of the primary circuit and the secondary circuit includes at least one detection circuit detecting a change in a current flowing through the rectifying element circuit to determine whether a potential corresponding to the second reference potential is lower than or equal to a potential corresponding to the first reference potential.

Abstract: According to various embodiments, there is provided a method for generating a reference clock signal, the method including discharging a capacitive element to a discharged state, when a reset signal has a predetermined reset state; charging the capacitive element from the discharged state to a first voltage, when a charge signal has a predetermined charge state; comparing the first voltage to a zero voltage, when a compare signal has a predetermined compare state; generating a second voltage based on the comparing of the first voltage to the zero voltage; generating a clock signal based on the second voltage, using an oscillator; and generating each of the reset signal, the charge signal and the compare signal, based on the clock signal.

Abstract: The current-to-voltage converter includes an input for the current to be converted, an output for the converted voltage, a current-to-voltage conversion resistor arranged between the output and a reference potential, a processing circuit including a transistor, the input being connected to the output via the transistor, a twin circuit including components identical to and disposed in a similar way to those of the processing circuit, a voltage follower connected at the input to the processing circuit and at the output to the twin circuit, and means for reinjecting the current at the output of the follower into the processing circuit.

Abstract: A power circuit includes a power source for providing electrical power and two driving transistors being disposed in parallel and receiving electrical power from the power source. Each of the two driving transistors includes a gate terminal, a source connection, and a kelvin source connection. The power circuit also includes a control voltage source having a first terminal and a second terminal. The control voltage source provides a control signal to the two driving transistors for determining driving currents through the two driving transistors. The first terminal is connected to the gate terminals of the two driving transistors, and the second terminal is connected to the kelvin source connections of the two driving transistors. The kelvin source connections of the two driving transistors are inductively coupled.

Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.

Abstract: A sensorless measurement device for filter capacitor current by using a state observer is provided. The sensorless measurement device comprises a chip, wherein the chip comprises the state observer. The state observer is configured to retrieve a filter-capacitor-voltage actual value and a direct current link (dc-link) voltage of a present sampling time. According to the filter-capacitor-voltage actual value and the dc-link voltage, the state observer is configured to output a filter-capacitor-voltage state variable value, a filter-capacitor-current state variable value, and a disturbance-voltage state variable value of a next sampling time. The filter-capacitor-current state variable value is an average current value without ripples.

Abstract: A switch drive and control arrangement may comprise a first transformer configured to receive a control signal, a second transformer configured to receive a clock signal, and a demodulator configured to receive the control signal and the clock signal from a switch controller, via the first transformer and the second transformer. The demodulator may be configured to output a demodulated signal in response to the control signal and the clock signal. A signal fault detector may be provided to determine a fault in at least one of the control signal and the clock signal. A switch may be turned off in response to a fault being detected in at least one of the control signal or the clock signal.

Abstract: A three-phase transmitter that sets voltages of first, second, and third output terminals based on first, second, and third signals. The transmitter includes a first transmitting section configured to set the voltage of the first output terminal based on the first and third signals; a second transmitting section configured to set the voltage of the second output terminal based on the first and second signals; and a third transmitting section configured to set the voltage of the third output terminal based on the second and third signals.

Abstract: A duty cycle correction device may be provided for correcting a duty cycle of an input signal. The device includes a first duty cycle correction circuit. The first duty cycle correction circuit receives the input signal. The first duty cycle correction circuit generates a first intermediate signal. The device includes a first programmable delay circuit. The first programmable delay circuit is controlled by a first delay control signal. The first programmable delay circuit receives the first intermediate signal. The first programmable delay circuit generates an output signal. The device includes a second duty cycle correction circuit. The second duty cycle correction circuit receives the input signal. The second duty cycle correction circuit generates a second intermediate signal. The device includes a second programmable delay circuit. The second programmable delay circuit generates a reference signal. The device includes a skew control arrangement operable for generating the first delay control signal.

Abstract: A vehicle includes a chassis, an engine coupled to the chassis, a primary electrical system, and an auxiliary electrical system. The primary electrical system is configured to power one or more electrical loads associated with operation of the vehicle when the engine is running. The primary electrical system includes a primary alternator and a primary battery. The auxiliary electrical system includes an auxiliary alternator configured to generate electrical power, a battery system electrically coupled to the auxiliary alternator and configured to store at least a portion of the electrical power generated by the auxiliary alternator, and an inverter coupled to the battery system. The inverter is configured to at least one of (a) charge the battery system, (b) power a direct current load, and (c) power an alternating current load.

Abstract: A wireless power feeding apparatus (100) is configured to perform wireless communication with a power reception side apparatus (200) and to perform wireless power transmission to the power reception side apparatus. The wireless power feeding apparatus is provided with: a communicating device (120) configured to switch between a first communication method that allows one-to-many communication and a second communication method that has less communication delay than the first communication method, thereby performing the wireless communication; and a communication controlling device (110) configured to control the communicating device to switch from the first communication method to the second communication method and to perform the wireless communication in the second communication method, on condition that the wireless power feeding apparatus becomes in a state in which the power transmission can be performed, when the communicating device performs the wireless communication in the first communication method.

Abstract: A device (10) for the electric power supply of a load (11), includes at least two energy storage elements (13, 14), elements for determining the power needs of the load (11), elements (16, 17) for monitoring each energy storage element (13, 14), which are able to provide information about a maximum instantaneous power of each energy storage element (13, 14), a calculation body (19) for determining a maximum secured power according to the electromotive force (Ebat(t)) and the resistance (Rbat(t)) of the Thévenin model, a maximum specified current and a maximum specified voltage, and elements (Cbat(t), Csc(t)) for controlling each energy storage element (13, 14), the elements being adjusted over time according to the power needs of the load (11) and the maximum secured power of each energy storage element (13, 14).

Abstract: An galvanic isolator circuit is provided. The electronic isolator circuit includes a coil and a magnetic field (MF) sensor. The coil is coupled to a first circuit. The MF sensor is coupled to a second circuit, and disposed corresponding to the coil. The first circuit transfers a MF signal to the MF sensor via the coil. The MF sensor transforms the MF signal into an output signal and provides the output signal to the second circuit. Accordingly, the galvanic isolator circuit is capable of realizing functions for galvanic isolating by utilizing the coil and the MF sensor.

Abstract: A clock calibration method of a navigation system is provided. The clock calibration method includes: entering a calibration mode; sequentially issuing, by a host, a count start signal and a count end signal separated by a time interval; counting a local oscillation frequency of a local oscillator when a navigation device receives the count start signal from the host; disabling the counting when the navigation device receives the count end signal from the host and generating a current count; generating a calibration signal according to the current count and a predetermined count corresponding to the time interval; and calibrating the local oscillation frequency of the local oscillator according to the calibration signal.

Abstract: A control circuit and a terminal are provided. The control circuit includes a detector, a current-voltage conversion circuit and a control signal generation circuit. The current output end of the detector is connected with the current input end of the current-voltage conversion circuit. The voltage output end of the current-voltage conversion circuit is connected with the voltage input end of the control signal generation circuit. The signal input end of the control signal generation circuit outputs a control signal. The detector detects a state of motion of a detected object and generates at least one current signal according to the state of motion of the detected object. The current-voltage conversion circuit converts the at least one current signal transmitted by the detector to at least one voltage signal.