Abstract: A digital phase-and-frequency controller. In one embodiment, the controller includes: (1) a first segment accumulator operable to accumulate errors while an accumulation-selection signal has a first value and (2) a second segment accumulator operable to accumulate errors while said accumulation-selection signal has a second value, and (3) circuitry operable to produce the control signal using the errors accumulated in the first segment accumulator while a use-selection signal has a first value and the errors accumulated in the second segment accumulator while the use-selection signal has a second value.

Abstract: According to one embodiment, a semiconductor amplifier circuit includes: a first amplifier circuit including first and second P-type transistors; a second amplifier circuit including first and second N-type transistors; and first to seventh current mirror circuits. The first and second current mirror circuits are connected to drains of the first and second P-type transistors. The third and fourth current mirror circuits are connected to drains of the first and second N-type transistors. The sixth current mirror circuit is connected to the first, fourth and fifth current mirror circuits. The seventh current mirror circuit is connected to the second, third and fifth current mirror circuits.

Abstract: In some examples, automatic light fixture address technology includes methods and apparatuses. In other examples, the method includes receiving a disable forward control command to disable data forwarding through the light fixture; receiving an enable forward control command to enable data forwarding through the light fixture; transmitting address data for the light fixture based on the enable forward control command; and forwarding one or more additional enable forward control commands based on the enable forward control command.

Abstract: A charge pump includes a charge pump core circuit, a replica bias circuit, and a differential amplifier. The charge pump core circuit includes current source and sink circuits for charging and discharging an output node of the charge pump core circuit. The current source and current sink circuits are user programmable using bit signals to adjust a bandwidth and a phase margin of a phase-locked loop (PLL) that includes the charge pump. An impedance of the replica bias circuit varies based on the bit signals. The differential amplifier and the replica bias circuit form a feedback loop that reduces current mismatch between the current source and sink circuits.

Abstract: A circuit for generating a voltage waveform at an output node. The circuit includes a voltage rail connected to the output node via a voltage rail switch; an anchor node connected to the output node via an inductor and a bidirectional switch, wherein the bidirectional switch includes two or more transistors connected in series; and a control unit configured to change the voltage at the output node by controlling the voltage rail switch and the bidirectional switch so that, if a load capacitance is connected to the output node, a resonant circuit is established between the inductor and the load capacitance. The circuit may be included in an apparatus for use in processing charged particles, e.g. for use in performing mass spectrometry or ion mobility spectrometry.

Abstract: A scan driving circuit configured for driving cascaded scan lines is provided, which includes an input control module, a latch module, a driving-signal generation module, an output control module, a constant high voltage source and a constant low voltage source. The scan driving circuit of the present invention drives the input control module through cascade signals of a preceding stage and cascade signals of a succeeding stage, so as to reduce interference and the driving power consumption of the scan driving circuit.

Abstract: In accordance with an embodiment of the present invention, a method of operating a voltage generator includes providing a bypass switch to bypass a ripple filter coupled to a power converter. A coupling capacitor includes a first plate and a second plate. The first plate is coupled to a control node of the bypass switch. A bypass control signal is received. The control node of the bypass switch is toggled between a first voltage to a second voltage different from the first voltage by toggling the second plate of the coupling capacitor based on the bypass control signal.

Abstract: A semiconductor device according to an embodiments controls a gate voltage to be applied to a gate electrode of a junction field effect transistor including a source electrode, a drain electrode, and the gate electrode, the transistor having a first threshold voltage at which the transistor is turned on, and a second threshold at which conductivity modulation occurs in the transistor so as to make the gate voltage equal to or higher than the second threshold voltage when a forward current in a direction from the drain electrode toward the source electrode flows, and so as to make the time variation in gate voltage have a point from which the rate of the time variation starts decreasing at a voltage between the second threshold voltage and the first threshold voltage when the forward current to be shut down.

Abstract: An adaptive driver includes a gate driver having at least one driving transistor for driving a control node of switching transistor(s) that includes an output node (OUT) which provides Vout. An adjustable current source is in series with the driving transistor, a high pass filter (HPF) is between OUT and ground for detecting a slew rate of the switching transistor and outputting a voltage pulse (Vslp) output having a peak voltage amplitude at least monotonically reflecting a slope of Vout during switching. Detection signal processing circuitry is coupled to the output of the HPF for processing Vslp and slew rate control circuitry has an input coupled to the output of the detection signal processing circuitry. The output of the slew rate control circuitry is coupled to the current source for controlling its current level for changing the slew rate of the switching transistor to provide a desired slew rate range.

Abstract: A parallel interface is disclosed. The parallel interface of the present disclosure includes an input unit configured to input, in parallel, a plurality of predetermined data signals and a clock signal; an output unit configured to output, in parallel, the predetermined data signals in synchronization with the clock signal; and a plurality of transmission lines disposed between the input unit and the output unit and configured to transmit, in parallel, the predetermined data signals and the clock signal, wherein the transmission lines are configured with a wiring pattern in which the transmission lines have different electrical lengths and an equal electrical capacitance.

Abstract: In various embodiments, a light-emitting apparatus is disclosed. In one example, the light-emitting apparatus comprises a substrate, an LED string mounted on the substrate, in which LED string a plurality of LEDs are connected in series, a power supply path connected in series to the LED string, and a plurality of protection elements, each protection element having a first node commonly connected to the power supply path and a second node connected between a pair of the LEDs in the series, wherein the protection elements include capacitors or zener diodes, and an AC impedance of each protection element is smaller than an impedance between the pair of LEDs and a case ground.

Abstract: Circuitry accepts an input signal and distributes the input signal to a plurality of locations within the circuitry. The circuitry includes a first circuit element and a second circuit element. The circuitry further includes a first plurality of wire segments that are substantially aligned to form a first bundle, and include a first wire segment. The circuitry further includes a second plurality of wire segments that are substantially aligned to form a second bundle, and have a second wire segment. An intersection element of the first bundle and the second bundle includes a first interconnecting wire segment that connects the first wire segment and the second wire segment, and the input signal is routed from the first wire segment to the second wire segment via the first interconnecting wire segment. The input signal is further transmitted to the second element from the second wire segment.

Abstract: Representative implementations of devices and techniques provide a speed increase to a comparator circuit. An active clamp device may be positioned between an input stage and an output stage of the comparator, limiting the voltage range of the output of the first stage.

Abstract: An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in an in-circuit mode or in a bypass mode. Embodiments of the invention allow for both a single switch in the series input path while still having the ability to isolate the bypass path from an input matching network. In both modes, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.

Abstract: Apparatus and methods for controlling radio frequency (RF) switches are disclosed. Provided herein are apparatus and methods for controlling RF switches. In certain configurations, an RF system includes a charge pump for generating a charge pump voltage, an RF switch, a level shifter for turning on or off the RF switch, and a level shifter control circuit for controlling the level shifter. The charge pump receives a mode signal used to enable or disable the charge pump. Additionally, the level shifter receives power in part from the charge pump voltage, and controls the RF switch based on a switch enable signal. The level shifter control circuit receives the mode signal and biases the level shifter with a bias voltage that changes based on a state of the mode signal.

Abstract: Provided are an output buffer circuit having an amplifier offset compensation function and a source driving circuit including the output buffer circuit. The output buffer circuit may include a plurality of channel amplifiers, each of which is configured to adjust an amount of current flowing through transistors connected to at least one of a non-inverted input terminal and an inverted input terminal of a differential input unit to compensate an amplifier offset, and adjust buffer input voltage signals to generate output voltage signals.

Abstract: According to an embodiment, an electronic circuit is described comprising a processing circuit, a power supply configured to supply power to the processing circuit via two supply nodes; a determiner configured to determine whether the voltage between the two supply nodes is above a predetermined reference voltage; and a clock generator configured to generate a clock signal for the processing circuit wherein the clock generator is configured to if the determiner determines that the voltage between the two supply nodes is again, after pausing the generation of clock edges, above the predetermined threshold the clock generator generates a clock edge irrespective of whether it is currently a time point given by the predetermined periodicity.

Abstract: A self clocking comparator for clocking a charge pump providing a high voltage output including multiple gain stages and a reset circuit. The gain stages are configured to assert the compare voltage at a first voltage level in a default state when the sense voltage is greater than the reference voltage, and to assert the compare voltage to a second voltage level in a reset state when the sense voltage falls below the reference voltage. The reset circuit resets, or otherwise forces, the gain stages back to the default state in response to the compare voltage transitioning to the second voltage level. The compare voltage oscillates while the sense voltage is less than the reference voltage at a frequency based on a magnitude of a difference between the sense voltage and the reference voltage up to a predetermined maximum frequency level.

Abstract: A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors.

Abstract: A lamp includes a lamp tube, a carrier, a light bar circuit board, a driver circuit board, a plurality of first luminous elements and a parallel-connected type luminous unit. The carrier is accommodated in the lamp tube. The light bar circuit board is disposed on the carrier. The driver circuit board is disposed on the carrier and adjoins the light bar circuit board. The first luminous elements are disposed on the light bar circuit board. The parallel-connected type luminous unit is disposed on the driver circuit board, and includes a plurality of luminous element groups connected in parallel.