Abstract: Embodiments in accordance with the present invention enable a disk drive of an address system to write data normally, wherein track groups of different track widths are discretely disposed on the storage medium in a same disk drive and the dimensional relationship among physical block addresses of a sector is valid for the dimensional relationship among logical block addresses. Track groups are managed corresponding to their respective track width in a disk drive and for disposing successively in a logical block address space the respective track groups located discretely on the physical block address space.

Abstract: Systems, apparatuses and methods for erasing hard drives. A system, which can be configured as a stand alone and portable apparatus, includes a control device configured to support an erase module. The erase module is configured to erase a hard drive such that data erased from the hard drive is forensically unrecoverable. The system further includes a user interface and at least one drive bay configured to provide communication between a hard drive and the control device.

Abstract: Some embodiments of the invention implement point-to-point memory channels that virtually eliminate the need for mandatory synchronization cycles for a derived clocking architecture by tracking the number of data transitions on inbound and outbound data lanes to make sure the minimum number of transitions occur. Other embodiments of the invention perform data inversions to increase the likelihood of meeting the minimum data transition density. Still other embodiments are described in the claims.

Abstract: A method is provided for use in a computer system for: (A) receiving notification of a virtual memory trap; (B) determining whether the virtual memory trap was triggered by an access to a region of memory identified as protected against access; (C) if it is determined that the virtual memory trap was triggered by an access to a region of memory identified as protected against access, determining whether the virtual memory trap was triggered by computer program code identified as suspect; and (D) if it is determined that the virtual memory trap was triggered by computer code identified as suspect, signaling a fault to a debugger executing on the computer system.

Abstract: A content addressable memory (CAM) device, method, and method of generating entries for range matching are disclosed. A CAM device (800) according to one embodiment can include a pre-encoder (806) that encodes range bit values W into additional bits E. Additional bits E can indicate compression of range rules according to particular bit pairs. A CAM array (802) can include entries that store compressed range code values (RANGE) with corresponding additional bit values (ENC). Alternate embodiments can include pre-encoders that encode portions of range values (K1 to Ki) in a “one-hot” fashion. Corresponding CAM entries can include encoded value having sections that each represent increasingly finer divisions of a range space.

Abstract: Provided are techniques for copying data. A volume container copyset that includes volume containers is received. A volume container copyset that includes volume containers is received. Each of the volume containers is associated with a copyset role, and each of the volume containers includes zero or more volumes, wherein each of the volumes in a volume container has the copyset role of that volume container. Sets of volumes are associated with a replication session, wherein each of the sets of volumes has one volume from each of the volume containers. Each of the sets of volumes has volumes associated with a copyset role that is associated with the volume containers with which each volume is associated. In response to determining that one of membership of one of the volume containers and a size of a volume in one of the volume containers has been modified, one or more corresponding volume containers in the volume container copyset are automatically modified.

Abstract: A method, system and computer program product for avoiding unnecessary grace period token processing while detecting a grace period without atomic instructions in a read-copy update subsystem or other processing environment that requires deferring removal of a shared data element until pre-existing references to the data element are removed. Detection of the grace period includes establishing a token to be circulated between processing entities sharing access to the data element. A grace period elapses whenever the token makes a round trip through the processing entities. A distributed indicator associated with each processing entity indicates whether there is a need to perform removal processing on any shared data element. The distributed indicator is processed at each processing entity before the latter engages in token processing. Token processing is performed only when warranted by the distributed indicator.

Abstract: A shared memory is usable by concurrent threads in a multithreaded processor, with any addressable storage location in the shared memory being readable and writeable by any of the threads. Processing engines that execute the threads are coupled to the shared memory via an interconnect that transfers data in only one direction (e.g., from the shared memory to the processing engines); the same interconnect supports both read and write operations. The interconnect advantageously supports multiple parallel read or write operations.

Abstract: A technique is described for managing the local storage of digital assets, such as audio, (moving or still) pictures, text, executable code and combinations thereof, in the storage device of a user appliance, such as a personal video recorder, set top box, mobile phone or storage server. A digital asset is received that is intended for local storage in the storage device and that has been pushed down from a source. A rank order is assigned to each digital asset stored or to be stored in a storage device that has a finite capacity storage space for storing digital assets. The assigned rank orders of one or more of the digital assets are repeatedly examined and a digital asset having a rank order that is lowest among the examined rank orders may be deleted. Each rank order is assigned based on predefined default ranking rules and user instructions pertaining to one or more of the digital assets that are capable of causing a deviation from the default ranking rules, if any have been provided by the user.

Abstract: Methods, systems, and computer program products for providing access to shared storage by a plurality of nodes are disclosed. According to one method, at a node of a plurality of nodes sharing access to a disk array, an application input/output (I/O) operation and whether sufficient space in the disk array has been mapped at the node for the I/O operation are detected. In response to detecting that sufficient space in the disk array has not been mapped at the node for the I/O operation, a map for the I/O operation including physical disk access information is requested and obtained from a server. The physical disk access information included within the map for the application I/O operation obtained from the server is used to perform the I/O operation by accessing the disk array without intervention by the server.

Abstract: A virtual storage control apparatus of the present invention writes data of a write request in an empty block of a virtual disk for data integrity to which any malicious access or false operation is not made, and records the time and the way of rewriting the data into the virtual disk by the write request on a rewrite information storage unit. When there is a data restore request for the virtual disk by designating a virtual disk and write time, the virtual storage control apparatus reads the data of the virtual disk at the write time from a virtual disk for data integrity, based on the information in the rewrite information storage unit, and restores the data of the virtual disk at the write time. With this configuration, the integrity of the data updated successively with the passage of time can be implemented.

Abstract: A processor includes a processor core coupled to an address translation storage structure. The address translation storage structure includes a plurality of entries, each corresponding to a memory page. Each entry also includes a physical address of a memory page, and a private page indication that indicates whether any other processors have an entry, in either a respective address translation storage structure or a respective cache memory, that maps to the memory page. The processor also includes a memory controller that may inhibit issuance of a probe message to other processors in response to receiving a write memory request to a given memory page. The write request includes a private page attribute that is associated with the private page indication, and indicates that no other processor has an entry, in either the respective address translation storage structure or the respective cache memory, that maps to the memory page.

Abstract: An interface device (D) is dedicated to debugging and/or tracing in a computer system (CS) comprising at least one master (M1, M2, M3) working with at least one slave (SLj) adapted to be readable and writable at chosen addresses, each master being adapted to execute tasks and to deliver slave addresses for reading and/or writing purposes. This interface device (D) comprises i) a group of first FIFO memories (SMi) each assigned to one master for storing data representative of the tasks it executes, ii) a group of dynamically allocatable second FIFO memories (DFk) linkable to one another and to the first FIFO memories (SFi), and iii) processing means (PM) arranged to compute dynamically the FIFO memory size required by each master at a given time, considering the tasks it is executing, and to allocate dynamically a number of second FIFO memories (DFk) to each master chosen according to the corresponding computed FIFO memory size.

Abstract: The invention concerns a system for saving data derived from a mainframe characterized in that it comprises a computer equipment including an input/output interface for exchanging data with the guest computer, said interface comprising a backup document reader/inscriber emulator, at least one intermediate storage device and a tape document reader/inscriber, the equipment further comprising a processor for transfer between the input/output interface or the intermediate storage device and the key-to-tape reader/inscriber, the system further including a supervisor comprising a storage unit for recording data concerning key-to-tape recordings of the computer equipment, and for controlling said computer equipment according to instructions coming from the guest computer.

Abstract: A method is disclosed to provide commands to an information storage and retrieval comprising one or more data storage devices, where one or more first communication links interconnect one or more host computers and the data storage and retrieval system. The method supplies a computing device, where that computing device is external to the data storage and retrieval system, and where that computing device is external to each of the one or more host computers. Applicants' method further supplies a second communication link interconnecting the computing device and the data storage and retrieval system. The computing device generates a command signal, where said command signal comprises one or more command control words and a header. The computing device then provides that command signal to the data storage and retrieval system via the second communication link.

Abstract: This invention discloses a system comprising a first comparator circuit configured to assert a first control signal in response to a first input number matching one of a first numbers stored therein, a second comparator circuit configured to assert a second control signal in response to: (i) at least one latched assertion of the first control signal; (ii) a second input number matching an intermediate number produced by incrementing the first input number; and (iii) an assertion of an input signal, and to de-assert the second control signal absent of either the matching between the second input number and the intermediate number or the de-assertion of the input signal, and a generator circuit configured to output a predetermined instruction data stored therein in response to the assertion of the first control signal, and to output a third number in response to the assertions of the second control signal.

Abstract: Data not stored in the DRAM array of a SDRAM module, such as the output of a temperature sensor, are read from the SDRAM in a synchronous read cycle that is seamlessly interspersed with SDRAM read and write cycles directed to data in the DRAM array. Control information, including a non-DRAM indicator in the case of data not stored in a DRAM array, are maintained for all read cycles. Returned data stored in a DRAM array and data not stored in a DRAM array are buffered together. When extracting read data from the buffer, data not stored in a DRAM array are identified by the non-DRAM indicator and directed to circuits within the controller. When data not stored in the DRAM array indicates the temperature of the SDRAM die, the controller may adjust the refresh rate in response to the temperature.

Abstract: In one embodiment, the present invention includes a method for maintaining a sequence of writes into a disk cache, where the writes correspond to disk write requests stored in the disk cache, and ordering cache writes from the disk cache to a disk drive according to the sequence of writes. In this way, write ordering from an operating system to a disk subsystem is maintained. Other embodiments are described and claimed.

Abstract: A method, system, computer system, and computer program product to allocate storage resources among multiple logical volumes. In response to a request to perform a set of operations on multiple logical volumes, a set of allocations of available storage space for performing the set of operations is made. At the time of identifying the storage regions to use for each allocation, the remaining operations and the storage regions that would be available for performing the remaining operations are examined. The rules for implementing each of the logical volumes can be evaluated as part of this examination. If it is apparent that one of the remaining operations will fail based upon a particular set of allocations, space allocated for a previous operation can be de-allocated and alternative allocations can be examined to find a set of allocations that enable the request to be performed successfully.

Abstract: For a virtual memory of a virtualized computer system in which a virtual page is mapped to a guest physical page which is backed by a machine page and in which a shadow page table entry directly maps the virtual page to the machine page, reverse mappings of guest physical pages are optimized by removing the reverse mappings of certain immutable guest physical pages. An immutable guest physical memory page is identified, and existing reverse mappings corresponding to the immutable guest physical page are removed. New reverse mappings corresponding to the identified immutable guest physical page are no longer added.