Abstract: A method for archiving data from a first disk-based storage device to a second disk-based storage device includes moving an emulated tape from a first element to a second element simulatively without actually moving data associated with the emulated tape. The data associated with the emulated tape is transmitted from the first disk-based storage device to the second disk-based storage device via a communication link. The data associated with the emulated tape is removed from the first disk-based storage device.

Abstract: An embodiment of the present invention is a technique to protect memory. A memory identifiers storage stores memory identifiers associated with protected components. The memory identifiers include exclusive memory identifiers and shared memory identifiers. The memory identifier storage is protected from access by a host operating system. A memory identifier management service (MMS) manages the memory identifiers. The MMS resides in a protected environment. An access control enforcer (ACE) enforces an access control policy with the memory identifiers.

Abstract: To provide a computer system, a management computer and a storage system, and a storage area allocation amount controlling method for improving I/O performance of the host computer. In a computer system comprising a storage system comprising one or more storage devices with storage areas, a host computer which uses a storage area of the storage device, and a management computer for dynamically allocating the storage area in response to an input/output request from the host computer; wherein the management computer monitors dynamic allocation of a real storage area to a storage area in the storage system, and calculates allocation increment amount to the allocated storage area based on the allocation frequency and the total amount of allocation.

Abstract: A content addressable memory (CAM) device (200) can provide for suppression of hit indications. Prioritized match indications (212) can be applied in parallel to both an encoding read-only-memory (ROM) (204-1) and suppression data store (206). A suppression data store (206) can output suppression bits (SH0 and SH1) that correspond to each CAM entry. Hit indications can be selectively suppressed according the values of suppression bits (SH0 and SH1). Hit suppression methods for a CAM device are also disclosed.

Abstract: A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n(n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.

Abstract: In a method and apparatus for encoding a bit field within a memory device, the bit field is encoded in a manner that requires fewer memory device entries and fewer encoded bits per entry than conventional encoding schemes.

Abstract: A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

Abstract: The apparatus, system and method implement subcontexts which associate groups of memory blocks. The apparatus, system and method maintain a permissions mapping for inter-subcontext memory accesses. A control module monitors all inter-subcontext memory accesses and prevents those accesses for which a permissions mapping does not exist.

Abstract: Methods, systems, and computer program products for postponing bitmap transfers and eliminating configuration information transfers during trespass operations in a disk array environment are disclosed. According to one method, a clone group is stored on a disk array, the clone group including a logical unit (LUN) representing a storage partition on the disk array and a clone of the LUN, the clone being a copy of the data referenced by the LUN. The clone group is associated with a first storage processor (SP) for writing data to the disk array. Changes between the LUN and the clone are tracked by maintaining a data structure indicative of the changes in a memory associated with the first SP. The association of the clone group is changed to a second SP for writing data to the disk array without transferring the data structure to memory associated with the second SP.

Abstract: The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200).

Abstract: An information processing apparatus comprising a secure information unit that is set to the state not requiring security in the case where the data is transferred from a user memory space to a general purpose register, and that is set to the state requiring security in the case where the data is transferred from a secure memory space to the general purpose register. An encryption key in the secure memory space is prevented from being stolen by prohibiting the data transfer to the user memory space from the general purpose register with the value of the secure information unit set to the state requiring security.

Abstract: System, method and computer program product for allocating physical memory to processes. The method includes enabling a kernel to free memory in a physical memory space corresponding to arbitrarily sized memory allocations released by processes or applications in a virtual memory space. After freeing the memory, the system determines whether freed physical memory in the physical memory space spans one or more fixed size memory units (e.g., page frames). The method further includes designating a status of the one or more page frames as available for reuse; the freed page frames marked as available for reuse being available for backing a new process without requiring the kernel to delete data included in the freed memory released by the process.

Abstract: A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the memory busses.

Abstract: A disk array control apparatus determines-whether or not a I/O process request from a host computer is causing a cache hit at a disk cache memory. The apparatus identifies the I/O process request as either high priority task or low priority task. The apparatus calculates a cache hit ratio. The apparatus executes only the high priority tasks when the cache hit ratio is high and executes both the high priority tasks and the low priority tasks when the cache hit ratio is low.

Abstract: A method and apparatus is disclosed for local access authorization of cached resources. A first request to perform an operation on a first object that is stored in a cache is received. An entity identifier associated with the entity that sent the first request, an operation identifier associated with the operation, and an Access Control List (ACL) associated with the first object are determined based on the first request. A record that includes at least the operation identifier, the ACL, and an authorization indicator is accessed. The authorization indicator indicates whether the entity has previously successfully performed the operation on any object in the cache that is associated with the ACL. Based on the authorization indicator included in the record, a determination is made whether to authorize the entity to perform the operation on the first object.

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, retrieve event data from a processor for sampling intervals, where the sampling intervals are evenly distributed, but the control points at which the event data is retrieved are unevenly distributed. The processor executes instructions for logical partitions, and the event data is associated with events that are detected by the processor during the sampling intervals. In response to an interrupt received from the processor at the control point, a determination is made whether the sample point has been reached. If the sample point has been reached, the event data is retrieved from the processor and an event counter is reset to a value that is calculated to cause the processor to include an identical number of the events in the sampling intervals. The value is calculated based on the event counter at the time control point, the event counter at a time of the sample point, and the number of events in the sampling interval.

Abstract: Methods and apparatus are provided for performing circular buffer addressing. Upper boundaries, lower boundaries, circular buffer lengths, addresses, and offsets are set to allow circular buffer access efficiency. An addition/subtraction unit is provided to simplify implementation. Comparators are rearranged and in some instances replaced with combined adder/comparator logic units. The additional logic units and the rearrangement allow efficient implementation of circular buffer addressing, particularly on programmable chips.

Abstract: A method for managing requests for deferred updates to shared data elements while minimizing grace period detection overhead associated with determining whether pre-existing references to the data elements have been removed. Plural update requests that are eligible for grace period detection are buffered without performing grace period detection processing. One or more conditions that could warrant commencement of grace period detection processing are monitored while the update requests are buffered. If warranted by such a condition, grace period detection is performed relative to the update requests so that they can be processed. In this way, grace period detection overhead can be amortized over plural update requests while being sensitive to conditions warranting prompt grace period detection.

Abstract: To enable favorable control of the storage of electronic information, a management device connected communicably to one or more storage control devices that are connected communicably to at least one of a plurality of storage devices refers to resource information relating to the usage condition of at least one hardware resource from among the one or more storage control devices, specifies an unused part of the hardware resource from the resource information, and sets a storage virtual computer, which serves as a virtual computer to which all or a part of the specified unused part is allocated, in at least one of the one or more storage control devices.

Abstract: Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In one embodiment, the invention includes receiving a first command at a memory device on a memory bus, the first command being other than a read or write command, and receiving a second command together with the first command, the second command to be initiated using lines that are not used by the first command.