Patents Examined by Michael C Krofcheck
  • Patent number: 7454581
    Abstract: A method for avoiding unnecessary grace period token processing while detecting a grace period without atomic instructions in a read-copy update subsystem or other processing environment that requires deferring removal of a shared data element until pre-existing references to the data element are removed. Detection of the grace period includes establishing a token to be circulated between processing entities sharing access to the data element. A grace period elapses whenever the token makes a round trip through the processing entities. A distributed indicator associated with each processing entity indicates whether there is a need to perform removal processing on any shared data element. The distributed indicator is processed at each processing entity before the latter engages in token processing. Token processing is performed only when warranted by the distributed indicator. In this way, unnecessary token processing can be avoided when the distributed indicator does not warrant such processing.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Paul F. Russell, Dipankar Sarma
  • Patent number: 7451288
    Abstract: Apparatus and method for generating an individual key for accessing a predetermined addressable unit of a memory divided into addressable units. The apparatus includes a calculator for calculating a page pre-key based on a page address, a determiner for determining the individual key based on the page pre-key and a unit address, a memory for storing the calculated page pre-key, and a checker for checking whether during a next access to a further predetermined unit to which a further unique address is associated, an already calculated page pre-key exists in a temporary memory, which has been calculated based on a page address of a unique address, which is identical to the page address of the further unique address, and, if so, transmitting the already calculated page pre-key to the determiner by bypassing the calculator, and, if not, transmitting the page address of the further unique address to the calculator.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: November 11, 2008
    Assignee: Infineon Technologies AG
    Inventors: Rainer Goettfert, Astrid Elbe, Berndt Gammel, Steffen Sonnekalb
  • Patent number: 7447855
    Abstract: A data processing system includes at least a first storage system, a second storage system and a third storage system. The third storage system maintains a replication of data stored in the first storage system. When updating data in the first storage system, the first storage system updates the replication of data stored in the third storage system and creates a journal. The journal is formed from a copy of data used for update and update information such as a write command for update, etc. The second storage system also maintains a replication of data stored in the first storage system. The second storage system obtains the journal, and updates data stored therein corresponding to data stored in the first storage system in the order of data update performed in the first storage system. When updating data stored in the third storage system corresponding to data stored in the first storage system, the third storage system creates a journal using data update numbers created in the first storage system.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: November 4, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhito Suishu, Yusuke Hirakawa, Yoshihiro Asaka
  • Patent number: 7444470
    Abstract: A storage device executes a program matching a removable storage medium. The device has a drive unit for reading the storage medium, a program memory for storing a program module required for processing of a storage device and a module list, a random access memory, and a processor for performing access processing of the data of the storage medium by referring to the module list and executing the program module. The processor reads the program module stored in the storage medium, develops the program module in the random access memory, and registers the read module in the module list.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: October 28, 2008
    Assignee: Fujitsu Limited
    Inventor: Satoshi Makita
  • Patent number: 7434000
    Abstract: In one embodiment, a processor comprises a cache and a cache miss unit coupled to the cache. The cache miss unit is configured to initiate a cache fill of a cache line for the cache responsive to a first cache miss in the cache, wherein the first cache miss corresponds to a first thread of a plurality of threads in execution by the processor. Furthermore, the cache miss unit is configured to record an additional cache miss corresponding to a second thread of the plurality of threads, wherein the additional cache miss occurs in the cache prior to the cache fill completing for the cache line. The cache miss unit is configured to inhibit initiating an additional cache fill responsive to the additional cache miss.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: October 7, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Jama I. Barreh, Manish K. Shah
  • Patent number: 7426612
    Abstract: Methods and apparatus for enforcing instruction-cache coherence are described herein. In an example method, a memory region of an instruction cache is initialized to form an initialized memory region prior to generating new code associated with the initialized memory region. Coherence code associated with the initialized memory region is generated. The new code associated with the initialized memory is generated. At least one of the new code and the coherence code is executed. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: September 16, 2008
    Assignee: Intel Corporation
    Inventor: Kevin Rudd
  • Patent number: 7424589
    Abstract: One embodiment of the present invention provides a method and a system for tracking memory usage of tasks in a shared heap. The system performs a full garbage-collection operation on the shared heap, during which a base memory usage is determined for each task. The system then periodically samples task state during execution to generate an estimate of newly allocated memory for each task. The base memory usage and the estimate of newly allocated memory for each task are combined to produce an estimate of current memory usage for each task. This estimate of current memory usage is used to determine whether a task is likely to be violating a memory quota. If so, the system triggers a remedial action, which can include: a full garbage-collection operation; a generational garbage-collection operation; or generation of a signal which indicates that a memory quota violation has occurred.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: September 9, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Oleg A. Pliss, Bernd J. W. Mathiske
  • Patent number: 7409518
    Abstract: A method and system for allocating blocks of disk in persistent storage to requesting threads. A primary data structure is provided for organizing and categorizing blocks of disk space. In addition, a secondary data structure is provided for maintaining a list of all active file system processes and blocks of disk space used by those processes. Blocks of disk space are assigned to pages. At such time as a thread may request allocation of disk space, both data structures are reviewed to determine if the requested disk space is available and to limit access of available disk space to a single page of memory to a single thread at any one time.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: August 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Boaz Shmueli, James J. Seeger, Jr., Jason C. Young
  • Patent number: 7398371
    Abstract: A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: July 8, 2008
    Assignee: QUALCOMM Incorporated
    Inventors: Erich Plondke, William C. Anderson, Lucian Codrescu
  • Patent number: 7383377
    Abstract: A pointer comparing unit determines whether a value of a writing pointer is identical to a value of a reading pointer. When it is determined that the value of the writing pointer is different from the value of the reading pointer, an inter-memory transfer unit reads data stored in a location where a data transfer apparatus reads transmission data from a transmission ring buffer, transfers the data to a reception memory, and writes the data in a location designated by the reading pointer of a reception ring buffer. When the inter-memory transfer unit completes writing of the data in the reception ring buffer, a reading-pointer updating unit updates the reading pointer.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: June 3, 2008
    Assignee: Fujitsu Limited
    Inventors: Nina Arataki, Sadayuki Ohyama, Yukiaki Kokubo
  • Patent number: 7139870
    Abstract: A method of operating a device having at least one solid-state memory and at least one spinning media memory for storing data includes from time-to-time, determining whether the device is in motion; and in response to determining that the device is not in motion, transferring frequently accessed data between the spinning media memory and the solid-state memory. An apparatus for use with a device includes at least one solid-state memory; at least one spinning media memory; and a controller configured to transfer frequently accessed data between the spinning media memory and the solid-state memory when the device is not in motion.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: November 21, 2006
    Assignee: Intermec IP Corp.
    Inventors: Stephen J. Kelly, Michael Dant