Abstract: Techniques are disclosed relating to filtering access to a content-addressable memory (CAM). In some embodiments, a processor monitors for certain microarchitectural states and filters access to the CAM in states where there cannot be a match in the CAM or where matching entries will not be used even if there is a match. In some embodiments, toggle control circuitry prevents toggling of input lines when filtering CAM access, which may reduce dynamic power consumption. In some example embodiments, the CAM is used to access a load queue to validate that out-of-order execution for a set of instructions matches in-order execution, and situations where ordering should be checked are relatively rare.

Abstract: A serverless application is provided to a cloud site of a cloud services provider. The cloud services provider offers backend services that include an object store and a database. Input/output (IO) writes sent to a volume of a block storage device at a production site are intercepted and aggregated. The aggregated IOs and metadata for the IOs are transmitted from the production site to the cloud site of the cloud services provider. Upon receipt of the aggregated IOs and metadata at the cloud site, the aggregated IOs are stored in an object in the object store at the cloud site, and a function of the serverless application is triggered to write the metadata to the database offered by the cloud services provider.

Abstract: The disclosure herein describes placing a delta component of a base component in a target fault domain. A delta component associated with a base component is generated. The generation includes selecting a first fault domain as a target fault domain for the delta component based on the first fault domain including a witness component associated with the distributed data object of the base component. Otherwise, the generation includes selecting a second fault domain as the target fault domain based on the second fault domain including at least one data component that includes a different address space than the base component. Otherwise, the generation includes selecting a third fault domain as the target fault domain based on the third fault domain being unused. Then, the delta component is placed on the target fault domain, whereby data durability of the distributed data object is enhanced, and available fault domains are preserved.

Abstract: In various embodiments, methods and systems for implementing a distributed metadata management system in distributed storage systems are provided. A distributed storage system operates based on data storage resources (e.g., extents and streams). The distributed metadata management system is implemented for extent and stream metadata to facilitate the scalability of metadata processing. The distributed storage system implements extent managers and stream managers that independently manage extent and stream metadata, respectively. The extent managers are associated with an extent table that stores extent metadata. The stream managers are associated with streams that store associations with extents. The distributed metadata management system can also utilize a bootstrap layer that leverages components of a legacy distributed storage system to facilitate distributed management of extent and stream metadata.

Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.

Abstract: Aspects include receiving a request from a requesting system to move data from a source memory on a source system to a target memory on a target system. The receiving is at a first hardware engine configured to access the source memory and the target memory. In response to receiving the request, the first hardware engine reads the data from the source memory and writes the data to the target memory. In response to the reading being completed, the first hardware engine transmits a data clearing request to a second hardware engine that is configured to access the source memory. The data clearing request specifies a location of the data in the source memory to be cleared.

Abstract: Techniques for efficiently purging non-active blocks in an NVM region of an NVM device using virtblocks are provided. In one set of embodiments, a host system can maintain, in the NVM device, a pointer entry (i.e., virtblock entry) for each allocated data block of the NVM region, where page table entries of the NVM region that refer to the allocated data block include pointers to the pointer entry, and where the pointer entry includes a pointer to the allocated data block. The host system can further determine that a subset of the allocated data blocks of the NVM region are non-active blocks and can purge the non-active blocks from the NVM device to a mass storage device, where the purging comprises updating the pointer entry for each non-active block to point to a storage location of the non-active block on the mass storage device.

Abstract: In a complex system including; one or more storage systems including a cache and a storage controller; and one or more storage boxes including a storage medium, the storage box generates redundant data from write data received from a server, and writes the write data and the redundant data to the storage medium. The storage box transmits the write data to the storage system when it is difficult to generate the redundant data or it is difficult to write the write data and the redundant data to the storage medium. The storage system stores the received write data in the cache.

Abstract: A method for safely sharing access to a volume is disclosed. In one embodiment, such a method includes notifying a storage system that a volume on the storage system is in use by a first host system. The method stores, on the storage system, a first indicator indicating the volume is in use by the first host system. When the storage system receives an I/O request from a second host system to access data on the volume, the storage system reads the first indicator to determine that the volume is in use by the first host system. The storage system may then reject the I/O request from the second host system as a result of the first indicator. A corresponding system and computer program product are also disclosed.

Abstract: Buffers in a buffer pool refer to memory locations either in local memory or in non-volatile memory used as persistent storage. The local memory and non-volatile memory have access latencies of the same order of magnitude, or a small multiple of each other. A buffer pool management system has operations to manage transitions between these states. Buffer cache copies can be avoided for read-only data, which can improve ramp-up times in database systems, increase cache capacity and improve performance of write operations. Power consumption can be reduced by avoiding memory copies and decreasing overprovisioning. These advantages can be obtained while making minimal, if any, changes to computer programs implementing the database server, particularly subsystems such as write-ahead logging and page replacement algorithms.

Abstract: A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.

Abstract: A multi-controller multi-memory device is disclosed. The device may include a plurality of controllers and a plurality memory units (m-units). Each controller is connected with a dedicated request-distribution unit (dist-unit) and a dedicated read-selection unit (read-unit). Each m-unit is connected with a dedicated arbitration unit (abt-unit). A controller's dedicated dist-unit is coupled with each of the abt-units dedicated to the plurality of m-units. The controller is configured to transmit a data-request to the controller's dedicated dist-unit, the data-request addressing an m-unit. The controller's dedicated dist-unit is configured to transmit the data-request to an abt-unit dedicated to the m-unit. The abt-unit is configured to select the data-request for transmitting to the m-unit based on an arbitration process.

Abstract: An apparatus (2) comprises processing circuitry (4) for performing data processing in response to instructions. The processing circuitry (4) supports a cache maintenance instruction (50) specifying a virtual page address (52) identifying a virtual page of a virtual address space. In response to the cache maintenance instruction, the processing circuitry (4) triggers at least one cache (18, 20, 22) to perform a cache maintenance operation on one or more cache lines for which a physical address of the data stored by the cache line is within a physical page that corresponds to the virtual page identified by the virtual page address provided by the cache maintenance instruction.

Abstract: The disclosure relates to a method for processing an application, an electronic device, and a computer-readable storage medium. The method is carried in an electronic device and includes that a plurality of reclaimable memory pages occupied by an application to be processed are determined; data stored in the plurality of reclaimable memory pages is written into an external storage medium; an operation of the application to be processed is paused; and the data written into the external storage medium is written into a memory when the operation of the application to be processed is unpaused.

Abstract: A data backup method and a data processing system are provided. The method includes: when a quantity of storage files stored in a storage medium meets a preset threshold, acquiring storage files which are stored in the storage medium after a time point, where the time point is a time of previously backing up storage files in the storage medium; combining the storage files after the time point to obtain at least one new storage file; and backing up the at least one new storage file. Therefore, incremental backup is performed on the storage files after the time point.

Abstract: A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.

Abstract: The disclosure relates to a method for processing an application, an electronic device, and a computer-readable storage medium. The method is carried in an electronic device and includes that a plurality of reclaimable memory pages occupied by an application to be processed are determined; data stored in the plurality of reclaimable memory pages is written into an external storage medium; an operation of the application to be processed is paused; and the data written into the external storage medium is written into a memory when the operation of the application to be processed is unpaused.

Abstract: An embodiment of an apparatus includes a plurality of processing circuits, a plurality of memory circuits, and a memory controller circuit coupled to each memory circuit via a respective communication channel. A particular processing circuit may generate a data stream that includes a plurality of data blocks. The memory controller circuit may receive the plurality of data blocks from the particular processing circuit. The memory controller circuit may distribute the plurality of data blocks among the plurality of memory circuits based on respective utilizations of the plurality of communication channels.

Abstract: Disclosed herein is method and system for managing storage space complexity in a storage unit. In an embodiment, operational parameters related to memory operations and storage parameters related to memory blocks of the storage unit are analyzed to estimate storage capacity of each of the memory blocks. Subsequently, the memory blocks are clustered into plurality of clusters based on the storage capacity. Further, one or more of the plurality of clusters are selected for performing future memory operations based on ranking of the plurality of clusters. In some embodiments, the present disclosure helps in dynamically managing storage space complexity in the storage unit and optimizes the storage space utilization. Also, the present disclosure automatically handles storage volumes, thereby reducing latency in memory backup operations and reducing amount of buffer/cache memory required.

Abstract: A processing system includes a memory controller coupleable to a RAM, and a ROM configured to store boot information that includes default values for a set of one or more memory timing parameters. At least one processor is configured to, during initialization, configure the memory controller to utilize the default values for the set of one or more memory timing parameters. The at least one processor further is configured to, during operation of the processing system following initialization, receive user input representing one or more updated values for one or more corresponding memory timing parameters of the set, and to dynamically reconfigure the memory controller to utilize one or more updated values for the set of one or more memory timing parameters for the signaling. The processing system further is configured to conduct one or more memory access operations for the RAM using the reconfigured memory controller.