Abstract: A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.

Abstract: In an example, a method of processing commands for a non-volatile storage device includes storing the commands among a plurality of first-level queues in a random access memory (RAM). Each command is assigned to a first-level queue based on membership in one of a plurality of first-level categories. The method further includes removing selected commands from the plurality of first-level queues according to a first schedule and performing at least one operation on the selected commands. The method further includes storing the selected commands among a plurality of second-level queues in the RAM. Each selected command is assigned to a second-level queue based on whether the command is a read command or a write command. The method further includes removing active commands from the plurality of second-level queues according to a second schedule. The method further includes issuing the active commands to a back end of the controller for processing.

Abstract: A cache apparatus is provided comprising a data storage structure providing N cache ways that each store data as a plurality of cache blocks. The data storage structure is organised as a plurality of sets, where each set comprises a cache block from each way, and further the data storage structure comprises a first data array and a second data array, where at least the second data array is set associative. A set associative tag storage structure stores a tag value for each cache block, with that set associative tag storage structure being shared by the first and second data arrays. Control circuitry applies an access likelihood policy to determine, for each set, a subset of the cache blocks of that set to be stored within the first data array.

Abstract: A cache memory and method of operating a cache memory are provided. The cache memory comprises cache storage that stores cache lines for a plurality of requesters and cache control circuitry that controls insertion of a cache line into the cache storage when a memory access request from one of the plurality of requesters misses in the cache memory. The cache memory further has cache occupancy estimation circuitry that holds a count of insertions of cache lines into the cache storage for each of the plurality of requesters over a defined period. The count of cache line insertions for each requester thus provides an estimation of the cache occupancy associated with each requester.

Abstract: According to one embodiment, a memory system stores write data received from a host to a shared write buffer for write destination blocks, acquires first write data for plural pages from the shared write buffer, and writes the first write data to a first write destination block by a first-step write operation. When receiving write data from the host in a state in which an empty region does not exist in the shared write buffer, the memory system discards write data in the shared write buffer in which the first-step write operation has been finished. In a case where the first write data do not exist in the shared write buffer when a second-step write operation of the first write data is to be executed, the memory system transmits a request to acquire the first write data to the host.

Abstract: A memory system includes a non-volatile memory device including a plurality of memory blocks; and a controller comprising a volatile memory and configured to: store a plurality of write data delivered from a host in the memory blocks to the plurality of memory blocks; and managing mapping information corresponding to the stored write data in the volatile memory, wherein the controller is configured to check whether the plurality of write data are grouped into a transaction, selectively set a transaction flag to the mapping information based on a check result; and selectively store the mapping information in the memory blocks when the transaction flag is not set.

Abstract: An embodiment includes a system, comprising: a processor configured to: read a stride parameter from a device coupled to the processor; and map registers associated with the device into virtual memory based on the stride parameter; wherein: the stride parameter is configured to indicate a stride between the registers associated with the device; and the processor is configured to map at least one of the registers to user space virtual memory in response to the stride parameter.

Abstract: Methods, systems, and programming for accessing data are described herein. In a non-limiting embodiment, a request associated with a key may be received. A memory chunk in a first memory site associated with the key may be located. An entry in the memory chunk corresponding to the key may be determined. A first pointer to the key corresponding to a first location of the key within a buffer at a second memory site may be obtained from the entry. The key stored at the first location may be retrieved from the buffer at the second memory site.

Abstract: Examples of techniques for controlling write requests to a memory structure having limited write ports are described herein. An aspect includes storing, in a first queue, write requests received from a first source having a first priority. Another aspect includes storing, in a second queue, write requests received from a second source having a second priority, wherein the second priority is lower than the first priority. Aspects also include identifying a selected queue from the first queue and the second queue based on a selection algorithm, which is a function of a state associated with the first queue and the second queue. Aspects further include forwarding a write request from the selected queue to a write port of the memory structure.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a read only memory (ROM), a central processing unit, and a random access memory (RAM). The memory cell array stores data related to operating conditions of the semiconductor memory device. The ROM stores data used to control an operation of the semiconductor memory device. The central processing unit controls the operation of the semiconductor memory device according to the data read from the ROM. The central processing unit reads the data related to the operating conditions from the memory cell array in response to a requested operation and then temporarily stores the read data related to the operating conditions in the RAM. The central processing unit further reads the data related to the data related to the operating conditions from the RAM for controlling the operation of the semiconductor memory device.

Abstract: A computer processing system with a hierarchical memory system having at least one cache and physical memory, and a processor having execution logic that generates memory requests that are supplied to the hierarchical memory system. The at least one cache stores a plurality of cache lines including at least one backless cache line.

Abstract: Systems and methods are disclosed for command status polling at a flash queue of a non-volatile memory device. The flash queue may be configured to perform polling on the status of flash operations without direct oversight from the data storage controller or firmware. In certain embodiments, a flash queue circuit may be configured to receive, from a data storage controller of a nonvolatile solid state memory (NVSSM) data storage device, one or more commands to access a flash memory of the NVSSM data storage device, each command of the one or more commands including one or more instructions. The flash queue circuit may execute the one or more commands to access the flash memory, evaluate a status response from the flash memory at the flash queue circuit, and re-execute a sequence of instructions of the one or more commands based on the status response.

Abstract: A distributed storage schemes manages implementation of QoS targets for IOPs across compute nodes executing applications, primary storage nodes storing a primary copy of a logical storage volume, and clone storage nodes. On the compute node, a maximum priority is assigned to a minimum number of IOPs in a queue within a time window from a time of receipt of a last unexecuted IOP. Other IOPs are assigned a minimum priority. On the storage node, maximum priority IOPs are assigned to high priority queues, from which IOPs are executed first, and low priority IOPs are assigned to low priority queues. Methods for determining the capacity of storage nodes and allocating storage requests are also disclosed.

Abstract: A method for zeroing guest memory of a VM during boot up, includes the guest OS attempts to set a page to zero. A page fault is generated and is handled by the hypervisor. The page is mapped by the hypervisor to a page in host memory, and is given to the guest. The guest OS attempts to set the next page to zero. Another page fault is generated the hypervisor unmaps the host memory page, and the second page is mapped to the same page. The hypervisor then gives the page to the guest, which contains all zeros. The process is repeated for remaining pages of the guest memory.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory cannot overwrite data written in a memory area. The controller controls writing/reading of data to/from the nonvolatile memory in response to a request from a host device. The controller includes a garbage collection processor and a garbage collection controller. The garbage collection processor executes garbage collection to reuse a memory area on the nonvolatile memory in which unnecessary data remain. The garbage collection controller stops the garbage collection executed by the garbage collection processor when the storage device is in a loaded state equal to or less than a threshold value.

Abstract: A memory device may be configured to leverage memory resources of a host computing device to efficiently transition between different power states. In some embodiments, the memory device stores resume data within a host memory buffer (HMB) before transitioning to a low-power state, and uses the resume data stored within the HMB to resume operation from the low-power state. The memory device may be configured to pre-populate the HMB with resume data prior to transitioning to the low-power state. In some embodiments, the disclosed memory device is configured to gradually resume from the low-power state, which may comprise resuming services of the memory device in the order such services are required during the resume process.

Abstract: A controller may include a memory suitable for caching write data and map data corresponding to the write data; and a processor suitable for flushing the cached map data in a memory device, and then storing the write data in the memory device, wherein the map data includes location information of the write data.

Abstract: In an example method, write commands for a solid-state storage medium having storage region are received. Selected write commands are filtered out according to criteria. The selected write commands are cached. Writing pursuant to the selected write commands is aggregated to within boundaries of one of the storage regions of the storage medium.

Abstract: Embodiments of the present invention provide a method and a system for managing a storage system. Specifically, in one embodiment of the present invention there is provided a method for managing a storage system, the method comprising: in response to receiving a write request for writing target data to the storage system, writing the target data to an intermediate address range in an intermediate storage area of the storage system; parsing, based on an address mapping of the storage system, a target address range associated with the write request so as to obtain an actual address range; and moving the target data from the intermediate address range to the actual address range. In one embodiment of the present invention there is further provided a corresponding system and apparatus.

Abstract: The failure of a storage unit in a storage array of a storage system may render the storage unit unresponsive to any requests. Any writes to the storage system that occur during the failure of the storage unit will not be reflected on the failed unit, rendering some of the failed unit's data stale. Assuming the failed unit's data is not corrupted but is just stale, a partial rebuild may be performed on the failed unit, selectively reconstructing only data that is needed to replace the stale data. Described herein are techniques for storing information that identifies the data that needs to be rebuilt. When the storage unit fails, the segment identifier associated with the last data segment written to the storage system may be stored. Upon the storage unit recovering, the storage system can rebuild only those data segments whose identifier is greater than the stored segment identifier.