Abstract: Provided is a method of manufacturing gallium nitride quantum dots. The method includes the steps of: preparing a gallium precursor solution by heating a mixture prepared by dissolving a gallium halide and an organic ligand in a solvent; heating the gallium precursor solution to obtain a heated gallium precursor solution; hot-injecting a nitrogen precursor into the heated gallium precursor solution at a heating temperature to produce gallium nitride; growing the gallium nitride while maintaining the heating temperature, thereby producing a growth-completed gallium nitride; and cooling a solution including the growth-completed gallium nitride to produce gallium nitride quantum dots in a colloid state.

Abstract: A method of manufacturing a semiconductor structure includes forming a precursor structure including a plurality of conductive pads on a substrate, an etch stop layer between the conductive pads, and an UBM layer on the conductive pads and the etch stop layer. A plurality of mask structures are formed on the UBM layer, and a plurality of openings are formed between thereof. Each of the mask structures is located on one of the conductive pads, and the openings expose a first portion of the UBM layer. A supporting layer is formed in the openings. The mask structures are removed to form a plurality of cavities exposing a second portion of the UBM layer. A conductive material layer is formed in the cavities. The supporting layer is removed. The first portion of the UBM layer is removed to form a plurality of conductive bumps separated from each other.

Abstract: A laser marking device includes a laser emission unit configured to emit a laser beam to a first surface of an object to be processed, and a pressing unit configured to press a second surface that is opposite to the first surface of the object to be processed to make the first surface of the object to be flat. The pressing unit includes a first pressing portion configured to press an edge area of the second surface in a contact manner, and at least one second pressing portion configured to press a middle area of the second surface in a non-contact manner to maintain a separation distance from the second surface within a certain distance.

Abstract: A method for fabricating a semiconductor device includes: forming a first conductive layer; forming a second conductive layer over the first conductive layer; forming a conductive line by etching the second conductive layer; etching a portion of the first conductive layer to form a plug head having the same critical dimension as the conductive line; forming a first spacer that covers the conductive line and the plug head; etching the remaining first conductive layer to form a plug body that is aligned with the first spacer, wherein the plug body have a greater critical dimension than the plug head; and forming a second spacer by performing a selective oxidation onto a side wall of the plug body.

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

Abstract: Disclosed are a display device and a method for repairing and detecting a thin film transistor of the display device. The display device includes a plurality of thin film transistors, a gate line, a data line, and a testing circuit. The testing circuit includes a first detection pad, a second detection pad, a third detection pad, a first detection metal wire, and a second detection metal wire. The first detection metal wire is connected to the second detection pad. The second detection metal wire has a first branch, a detection metal pad, and a second branch. The first branch connects the first detection pad and the detection metal pad. The second branch connects the third detection pad and the detection metal pad. The detection metal pad overlaps with the first detection metal wire in a vertical direction. The first detection metal wire has a width same as that of the gate line, and the detection metal pad has a width same as that of the data line.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A memory device is described. A first conductive layer extends in a first direction. A second conductive layer extends in the first direction. A third conductive layer extends in a second direction intersecting the first direction. A first oxide region is disposed between the first conductive layer and the third conductive layer and between the second conductive layer and the third conductive layer. A semiconductor region is disposed between the first conductive layer and the first oxide region and between the first conductive layer and the second conductive layer. A second distance between the semiconductor region, which is disposed between the first conductive layer and the second conductive layer, and the third conductive layer, is longer than a first distance between the semiconductor region, which is disposed between the first conductive layer and the first oxide region, and the third conductive layer.

Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.

Abstract: A method for doping fins includes, for a first dopant layer formed in a first region and a second region to a height continuously below a top portion of a plurality of fins such that an entirety of the first dopant layer is formed below the top portion of the plurality of fins, and a dielectric layer formed over the top portion of the plurality of fins, removing the dielectric layer and the first dopant layer in the first region to expose a first fin in the first region, forming a second dopant layer over the first fin, and annealing to drive dopants into the fins from the first dopant layer in the second region and from the second dopant layer in the first region.

Abstract: A white organic electroluminescent (EL) element includes, in sequence, an anode, a first light-emitting layer that is a blue-light-emitting layer, a hole-blocking layer, an electron transport layer, and a cathode. The hole-blocking layer is adjacent to the first light-emitting layer and the electron transport layer and formed of a hydrocarbon. The electron transport layer is formed of a nitrogen-containing heterocyclic compound. The first light-emitting layer contains a first host and a first dopant that emits blue fluorescent light. Relations (a), (b), and (c) are satisfied. LUMO(H1)>LUMO(D1)??(a) 0.1<d(ETL)/d(HBL)<0.7??(b) 90 nm?d(E)=d(HBL)+d(ETL)<150 nm??(c) LUMO (H1): lowest unoccupied molecular orbital (LUMO) energy of first host LUMO (D1): LUMO energy of first dopant d (HBL): thickness of hole-blocking layer d (ETL): thickness of electron transport layer.

Abstract: Provided herewith is a method for manufacturing the display screen, which includes sequentially forming a switch array layer and an organic light-emitting display layer on a flexible substrate; forming a first encapsulation layer on the organic light-emitting display layer; defining a first portion of a via hole in the first encapsulation layer; forming a second encapsulation layer in the first portion of the via hole and on the first encapsulation layer; removing a part of the second encapsulation layer corresponding to a position of the preset camera hole; defining a second portion of the via hole in the flexible substrate to obtain the via hole completely. Since the inner wall of the via hole of the camera of the disclosure is provided with the encapsulation layer, the encapsulation effect and the reliability of the encapsulation are improved.

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

Abstract: The present disclosure provides a method for preparing a semiconductor structure. The method includes the following steps. A substrate including a conductive layer formed thereon is provided. The conductive layer is patterned to form a plurality of conductive patterns extending along a first direction. A cap layer is conformally formed to cover the plurality of conductive patterns. A patterned hard mask is formed over the cap layer. The plurality of conductive patterns are etched through the patterned hard mask to form a plurality of conductive islands. In some embodiments, the plurality of conductive islands are separated from each other by a plurality of first gaps along the first direction. In some embodiments, the plurality of conductive islands are separated from each other by the cap layer and a plurality of second gaps along a second direction that is different from the first direction.

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.