Patents Examined by Michael Maskulinski
  • Patent number: 10977144
    Abstract: A memory system includes: a nonvolatile memory device including a plurality of memory blocks and spare blocks; and a memory controller configured to control the nonvolatile memory device. The nonvolatile memory device may store spare information to any one block of the memory blocks or the spare blocks. When a bad block is detected from the memory blocks, the nonvolatile memory device replaces the bad block with any one of the spare blocks according to the spare information.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Chi Eun Kim, Soo Nyun Kim
  • Patent number: 10970148
    Abstract: Embodiments of the present disclosure provide a method, device and computer program product for managing an input/output (I/O) stack. The method comprises obtaining metadata related to an I/O request stored in the I/O stack, the metadata at least comprising a timestamp when the I/O request is placed in the I/O stack; determining, based on the timestamp, a length of time during which the I/O request waits for processing; and in response to the length of time exceeding a threshold time length, performing a predetermined operation on the I/O request to prevent the I/O stack from being congested.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: April 6, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Bing Liu, Man Lv
  • Patent number: 10956287
    Abstract: Provided are techniques for implementing shared Ethernet adapter (SEA) failover, including receiving a first ARP packet at a first SEA coupled to a first switch; parsing, by the first SEA, a first MAC address and VLAN ID (VID) corresponding to the first ARP packet; transmitting the first MAC address and VID to a second SEA coupled to a second switch; detecting the first SEA has transitioned from a primary configuration to an inactive configuration and the second SEA has transitioned from a backup configuration to the primary configuration; and responsive to the detecting, transmitting a reverse ARP packet to the second switch notifying the second switch that the first SEA has transitioned to an inactive configuration and that the second SEA has transitioned to an active configuration; and configuring the first switch to forward any subsequent packets to the second switch rather than the first SEA.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Juliet M. Kim
  • Patent number: 10949277
    Abstract: Provided are a computer program product for managing bus interface errors in a storage system coupled to a host and storage. A determination is made as to whether a first number of correctable errors on a first bus interface, connecting a first processing unit to the storage, exceeds a second number of correctable errors on a second bus interface, connecting a second processing unit to the storage, by a difference threshold. The correctable errors in the first and second bus interfaces are detected and corrected in the first and second bus interfaces by first hardware and second hardware, respectively. In response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, at least a portion of Input/Output (I/O) requests are redirected to a second processing unit using the second bus interface to connect to the storage.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 10929220
    Abstract: Methods and systems for detecting and correcting anomalous behavior include generating a joint binary embedding of each of a set of historical time series sequences. A joint binary embedding of a recent time series sequence is generated. A ranked list of the plurality of historical time series sequences is generated according to respective similarities of each historical time series sequence to the recent time series sequence based on the respective joint binary embeddings of each. Anomalous behavior of a system associated with the recent time series sequence is determined according to a label of a top-ranked historical time series sequence in the ranked list. A corrective action is performed to correct the anomalous behavior.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: February 23, 2021
    Inventors: Dongjin Song, Ning Xia, Haifeng Chen
  • Patent number: 10929230
    Abstract: Techniques manage a storage system. The storage system includes at least one part of multiple storage devices, here respective storage devices among the multiple storage devices include a first portion and a second portion, the first portion is for storing data and the second portion is reserved for rebuilding the storage system. The techniques involve: determining a storage device in the at least one part of storage devices fails; recovering data in a first portion of the failed storage device on the basis of data in a first portion of a normal storage device other than the failed storage device in the at least part of storage devices; selecting a group of storage devices from normal storage devices among the multiple storage devices; and writing recovered data to a second portion in the group of selected storage devices. Thereby, the speed of rebuilding the storage system may be increased, and further the overall performance of the storage system may be enhanced.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: February 23, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Jibing Dong, Xinlei Xu, Geng Han, Jianbin Kang
  • Patent number: 10922185
    Abstract: Systems and methods of error handling in a network interface card (NIC) are provided. For a data packet destined for a local virtual machine (VM), if the NIC cannot determine a valid translation memory address for a virtual memory address in a buffer descriptor from a receive queue of the VM, the NIC can retrieve a backup buffer descriptor from a hypervisor queue, and store the packet in a host memory location indicated by an address in the backup buffer descriptor. For a transmission request from a local VM, if the NIC cannot determine a valid translated address for a virtual memory address in the packet descriptor from a transmit queue of the VM, the NIC can send a message to a hypervisor backup queue, and generate and transmit a data packet based on data in a memory page reallocated by the hypervisor.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: February 16, 2021
    Assignee: Google LLC
    Inventors: Prashant Chandra, Ian Mclaren, Jon Olson, Jacob Adriaens
  • Patent number: 10922177
    Abstract: Embodiments of the present disclosure relate to method, device and computer readable storage media for rebuilding redundant array of independent disks (RAID). The method comprises: in response to detecting at least one fault disk in the RAID, adding a new disk to the RAID for rebuilding; determining, according to a mapping table, a first set of storage blocks marked as “free” in the at least one fault disk, the mapping table indicating usage state of storage space in the RAID; and writing a predetermined value into a second set of storage blocks corresponding to the first group of storage blocks in the new disk.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: February 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Shaoqin Gong, Jian Gao, Xinlei Xu, Geng Han, Jibing Dong
  • Patent number: 10922161
    Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Bryan White, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Mahesh Natu
  • Patent number: 10915387
    Abstract: A circuit assembly for monitoring the timing behavior of a microcontroller, including: a microcontroller to drive at least one watchdog voltage generating section for a temporally defined generation of at least one monitoring voltage and to detect and read in the generated monitoring voltage at a predetermined sampling point in time; in which the at least one watchdog voltage generating section is arranged to generate the monitoring voltage that is detectable at a predetermined sampling point in time by sampling by the microcontroller, in which a monitoring voltage that is detected at the sampling point in time and lies within a predetermined voltage tolerance range indicates a fault-free microcontroller state, and a monitoring voltage that is detected at the predetermined point in time and lies outside the predetermined voltage tolerance range indicates a faulty microcontroller state. Also described is a related method.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: February 9, 2021
    Assignee: KNORR-BREMSE SYSTEME FUER NUTZFAHRZEUGE GMBH
    Inventors: Wolfgang Gscheidle, Thorsten Beyse
  • Patent number: 10915415
    Abstract: Techniques and mechanisms for exchanging debug information with a repeater and multiplex logic of a platform. In an embodiment, the multiplex logic can be configured to any of multiple modes including a first mode to exchange debug information between the repeater and debug client logic of the platform. Another of the multiple modes may provide an alternate communication path for exchanging functional data, other than any debug information, between the repeater and a physical layer interface of the platform. In another embodiment, the repeater is compatible with a repeater architecture identified by a universal serial bus standard. The physical layer interface is compatible with an interface specification identified by the same universal bus standard.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: February 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Amit Kumar Srivastava, Huimin Chen
  • Patent number: 10908985
    Abstract: An image display apparatus and a driving method thereof are provided. The image display apparatus includes a memory including instructions; and a processor configured to execute the instructions to: in response to a request for executing a designated application being received, identify a type of error occurred in the image display apparatus, and based on the type of error identified by the processor, determine whether to: execute the designated application and recover from the error after the designated application is executed by the processor, or recover from the error and execute the designated application after recovering from the error.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoojin Park, Cheulhee Hahm
  • Patent number: 10877864
    Abstract: A processor memory is stress tested with a variable link stack depth using test code segments and link stack test segments on non-naturally aligned data boundaries. Link stack test segments are interspersed into test code segments of a processor memory test to change the link stack depth without changing results of the test code. The link stack test segments include branch to target, push/pop, push and pop segments. The depth of the link stack is varied independent of the memory test code by changing the number to branches in the branch to target segment and varying the number of the push/pop segments. The link stack test segments and test segments may be placed randomly with a recursive algorithm to intersperse the link stack test segments in the test code segments and to reduce the amount of data to be saved and restored for all subroutine calls, push and pop segments.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Shakti Kapoor, Manoj Dusanapudi
  • Patent number: 10877859
    Abstract: A system for monitoring a virtual machine executed on a host. The system includes a processor that receives an indication that a failure caused a storage device to be inaccessible to the virtual machine, the inaccessible storage device impacting an ability of the virtual machine to provide service, and applies a remedy to restore access to the storage device based on a type of the failure.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: December 29, 2020
    Assignee: VMware, Inc.
    Inventors: Joanne Ren, Igor Tarashansky, Keith Farkas, Elisha Ziskind, Manoj Krishnan
  • Patent number: 10860402
    Abstract: Serving resources. A method includes sending a message to a client indicating that the client should attempt to obtain status information for one or more asynchronous read/write operations on a datastore, requested by the client but not yet completed, at a later time. A request is received from the client for status information about the asynchronous, read/write, storage operations on the datastore. A message is sent to the client indicating that the asynchronous read/write operations are in progress and that the client should attempt to obtain status information for the asynchronous read/write operations on the datastore at a later time. Requests are received from the client for status information about the operations until the asynchronous read/write operations are complete, after which, an indication is provided to the client indicating that the asynchronous read/write operations have been completed.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: December 8, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Shyama Prasad Hembram, Gustavo Rafael Franco
  • Patent number: 10853212
    Abstract: A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Daniel S. Froelich
  • Patent number: 10853206
    Abstract: A main data center with first and second backup data centers also has a translator for assisting a failover module of a failed server at the main data center in implementing failover of the failed server to a corresponding server at the first backup data center. The translator intercepts a command from the failover module to a store of the main data center, where the command directs the store to disable writes to particular storage space in the store associated with the failed server, but does not identify with specificity which of a store of the first data center and a store of the second data center is enabled to write to such particular storage space. Thus, the translator determines an identification of the store of the first backup data center, and modifies the command from the failover module based on the determined identification.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: December 1, 2020
    Assignee: United Services Automobile Association
    Inventor: Larry S. Roy
  • Patent number: 10846025
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. A computing device receives a data access request for an encoded data slice (EDS) associated with a data object. The computing device compares a slice name of the data access request with slice names stored within RAM. When the data access request slice name compares unfavorably with those stored slice names, the computing device transmits an empty data access response that includes no EDS to the other computing device without needing to access a hard disk drive (HDD) that stores EDSs. Alternatively, the computing device transmits a data access response that includes the EDS.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 24, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Bruno Hennig Cabral, Joseph M. Kaczmarek, Ravi V. Khadiwala, Ilya Volvovski
  • Patent number: 10838801
    Abstract: A computer-implemented method for ranking and presenting actions executed by prior users when an error scenario occurs in a computer system is provided. The computer-implemented method includes identifying an error with the computer system and entering an error state with respect to the error. The computer-implemented method includes recording operations within the computer system during the error state and exiting the error state based on an exit condition.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin T. Rau, Dwight E. Allen, Jr., Scott D. Malzahn, Grant S. Mericle
  • Patent number: 10838832
    Abstract: During a synchronization technique, states of a primary cluster in the computer system with multiple primary controllers that provide controllers for access points and a backup cluster in the computer system with multiple backup controllers that independently provide controllers for the access points may be dynamically synchronized. In particular the primary cluster may receive configuration requests with configuration information for the access points on an input node of the primary cluster. In response, the primary cluster may store the configuration requests in a replay queue in the computer system. Then, the primary cluster may playback the configuration requests in the replay queue for the backup cluster to synchronize the states of the primary cluster and the backup cluster. For example, the configuration requests may be played back within a time interval associated with a service level agreement of a service provider of a service for the access points.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 17, 2020
    Assignee: ARRIS Enterprises LLC
    Inventors: Sudip Ghosal, Yi-Nan Lee