Abstract: A method and apparatus for observing the contents on internal memory-mapped registers of controllers and co-processors which have been integrated on-chip with a central processing unit ("CPU"). The CPU asserts a first signal when access to internal memory is requested and deactivates a second signal which would normally allow simultaneous access to both internal and external memory locations. In this way, the contents of internal memory may be observed in real time.

Abstract: A neutral network representing apparatus includes a plurality of neuron expressing units and a plurality of synapse load expressing units. Each of the synapse load expressing units couples two neuron expressing units through a synapse load which is specific thereto. The synapse load of the synapse load expressing unit is adjusted in accordance with a prescribed learning rule in learning of the neural network representing apparatus. This learning rule includes a learning coefficient which defines the amount of a synapse load to be changed in a single learning cycle. This learning coefficient is set according to a spatial or physical distance between two neurons expressed by two neuron expressing units which are coupled by a synapse load expressing unit. The learning coefficient is provided by a monotone decreasing function of the distance between the two neurons.

Abstract: A multiple-CPU system including a main CPU and at least one subordinate CPU connected thereto. Both the main and subordinate CPU are provided with a respective voltage detector circuit for detecting when a main or primary power supply voltage for the CPU's has dropped below a predetermined threshold level. When the respective detector circuit outputs a signal indicating detection of the drop in main power supply voltage, the respective CPU is placed in a standby state. However, the threshold level of the detector circuit of the main CPU is set to a voltage lower than the threshold level of the detector circuit of the subordinate CPU. As a result, the subordinate CPU is placed in a standby state before the main CPU. The main CPU is equipped with an auxiliary power supply so that when the subordinate CPU is placed in a standby state, automatic recovery is thereafter carried out by the main CPU.

Abstract: In the present invention, a communication system is disclosed. The communication system comprises a remote computer 20 and a local computer 40, linked by communication link 12. The local computer 40 operates a conventional alphanumeric communication program 42 which receives alphanumeric data from the remote computer 20. The local computer 40 also comprises a supervisory program 56 which is Terminate and Stay Resident in memory, and which interrupts the operation of the alphanumeric communication program 42. When a particular command query is generated from the remote computer 20, the supervisory program 56 causes the local computer 40 to respond thereto, indicating the capabilities of the local computer 40 for graphical data display.

Abstract: A synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided.

Abstract: In a cache memory simultaneously conducting updating for a miss and a decision on a miss for the subsequent address, a write flag generated by a control unit is written in a valid flag field. Based on this operation, during an access to an external memory at an occurrence of a miss, a tag field and the valid flag field are simultaneously updated. When updating a data field, a read operation is achieved on the tag and valid flag fields to decide occurrence of miss. Thus, an external memory access for a miss at a next address can be executed at an earlier point of time. Moreover, by the provision of a data latch disposed for an output from the data field, and by reading data at a next address and keeping it in the data latch during a memory read cycle, succeeding hit data can be outputted immediately after a miss processing is completed.

Abstract: A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitry. The interprocessor communications facility of the invention is centralized and does not require the use of main storage. This enables processors to communicate with each other in a fast and efficient manner. The arbitration circuitry prevents simultaneous access of the interprocessor communications facility by more than one processor, and decodes the commands sent from the processors and routes them to the processor interrupt circuitry or to the mailbox circuitry, depending on the command. The mailbox circuitry of the invention receives messages from sending processors and provides them to the intended receiving processors in a safe and secure manner.

Abstract: A control for robots wherein a plurality of control units are connected in a hierarchical structure including a plurality of ranks including the lowest rank, and the robots subordinate to the control units belonging to the lowest rank.

Abstract: The invention provides a pseudo set-associative memory cacheing arrangement for use in a data processing system comprising a processor interfacing to a main memory and adapted to support a cache memory. The arrangement comprises a plurality of cache memory banks each comprising a respective number of addressable locations individually defined by a cache address. A plurality of cache select circuits are each associated with a respective one of the cache memory banks and each one is responsive to m most significant bits of a main memory address and control signals for mapping its associated cache memory bank to a predetermined range of addresses in main memory.

Abstract: A method for resolving access contentions by a plurality of processing sites having the same or different redundancies to a shared communications system wherein the start of the access contention process is first synchronized for all contending sites. A determination is then made of which sites are performing tasks of the highest criticality level and a subsequent determination is made as to which of such highest criticality sites has the highest priority level. Access is then provided to the site having the highest priority level.

Abstract: In a digital computer, a method for speech recognition includes steps of sampling a speaker's speech and providing speech data sample segments of predetermined length at predetermined sampling intervals based on changes in energy in the speech. Cohesive speech segments, which correspond to intervals of stable vocoids, changing vocoids, frication, and silence, are identified from the speech data sample segments, and are assigned frames of subsyllables. Each cohesive segment corresponds to at least one respective frame, and each frame includes at least one of a plurality of subsyllables that characterizes predetermined gross and fine phonetic attributes of the respective cohesive segment. The subsyllables are located in a first lookup table mapping sequences of subsyllables into syllables, and the syllables are combined into words by locating words in another lookup table. The conformance of sequences of the words to a set of predetermined checking rules is checked, and a recognition result is reported.

Abstract: Method and apparatus are provided for use in a frame-based semantic network wherein at least one specialization slot-control frame defining a specialized behavior is linked to a base slot-control frame defining a global behavior in a hierarchical data structure. Slot behavior is attached to an occurrence of the slot in any other frame such that the slot and its behaviors are inherited to related frames as a unit. All specialized behaviors are compiled into a compact internal format and stored in a reserved space in the slot-control frame. The method and apparatus have particular utility in knowledge-based or expert systems.

Abstract: An artificial neural network is provided using a digital architecture having feedforward and feedback processors interconnected with a digital computation ring or data bus to handle complex neural feedback arrangements. The feedforward processor receives a sequence of digital input signals and multiplies each by a weight in a predetermined manner and stores the results in an accumulator. The accumulated values may be shifted around the computation ring and read from a tap point thereof, or reprocessed through the feedback processor with predetermined scaling factors and combined with the feedforward outcomes for providing various types neural network feedback computations. Alternately, the feedforward outcomes may be placed sequentially on a data bus for feedback processing through the network.

Abstract: A knowledge processing system in which a grade representing a degree at which an event is satisfied or unsatisfied is obtained depending on a condition part represented in a form of a logical arithmetic expression including an expression of a fuzzy logic and on a grade of satisfaction of the condition part generates rules on assumption of unmeasurable events associated with states of the external field of the system so as to add the rules to the rules related to the unmeasurable events. Forecast of a value of a measurable event is more correctly achieved depending on grades of satisfaction of the unmeasurable events and grades of satisfaction of measurable events. A warning may also be issued according to the forecasted value.

Abstract: A fault tolerant network for a plurality of computers includes a system for controlling access to shared peripherals. Access to the shared peripherals is coordinated among the computers by means of communication through a semaphore box. Each computer connects to the semaphore box via a channel. The semaphore box is comprised of two major sections: a semaphore section and an I/O section. The semaphore section contains two sets of semaphores: a first set comprising reservation semaphores for the shared peripherals; and a second set comprising heartbeat semaphores for the sharing computers. The first set is used to reserve a particular peripheral for a particular computer and indicate the source of the reservation; the second set provides a "heartbeat" to prevent reservation semaphores from being set indefinitely in the event communication with a particular computer is lost.

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface.

Abstract: A data communication system having serial data communication circuits and interrupt data communication circuits and allowing a plurality of CPUs to interchange data with each other. While a pluality of different kinds of data are interchanged by serial communication which occurs at predetermined intervals, only urgent data is interchanged by interrupt signals particular to interrupt communication. Whether or not to validate an interrupt signal (whether or not to mask an interrupt) is determined on the basis of data sent by serial data communication.

Abstract: A device information interface for a channel to channel I/O device having a plurality of channel adapters. A device interface bus interconnects each of the channel adapters, permitting an exchange of data between channel adapters. A virtual device storage array at each channel adapter stores the status of inactive channel devices associated with a connected channel. Inquiries as to the status of a logical adapter may be sent over the device interface bus. Logic circuits at the receiving adapter will decode the inquiry and address the virtual storage array to obtain the status of the logical adapter for forwarding over the bus to the inquiring adapter.

Abstract: A system and method for specifying a computer program. The specified computer program comprises a set of selected program objects, represented by a corresponding set of outline items arranged in a multilevel outline format. These outline items collectively and completely denote the nature and operation of the specified computer program. Each outline item has a set of predefined characteristics, including a set of required children, and a set of optional children, comprising outline items that must/may be included at the next lower outline level when this outline item is used in a computer program. For each outline item in a computer program an expansion denoting flag denotes whether the corresponding outline item has children and whether the display of those children has been enabled. A selected contiguous portion of the multilevel outline is shown on the computer system's display device, showing only outline items whose display is enabled by corresponding expansion display denoting flags.

Abstract: A device for sound synthesis intended to generate a desired acoustic signal includes a first signal source which emits a periodic signal having a given repetition frequency as a representation of the voiced parts of the desired acoustic signal, a second signal source which emits an aperiodic signal or a noise signal as a representation of the unvoiced parts of the desired sound signal, a combination circuit which combines the signals of the two signal sources with each other, and a filter circuit having a variable transmission function for processing the combined signal into the desired output signal. A third signal source emits a modulated noise signal consisting of a train or sequence of noise bursts of comparatively short duration, whose temporal envelope is synchronous with the temporal envelope of the periodic signal and which invariably have at least approximately the same energy.