Abstract: In a computer system having a storage unit for storing at least one of a program and knowledge used for solving a problem, an input/output unit for inputting a problem to be presently solved, and an execution unit for obtaining a proposed solution of one of the problem to be presently solved and a partial problem of the problem, by using at least one of the program and knowledge in the storage unit, an inference processing method includes the steps of storing a modification case generated upon modification of a solution, calculating a portion, unable to be solved by the proposed solution obtained by the execution unit, of one of the problem to be solved and the partial problem, searching for a modification case containing a problem similar to the unsolved portion, from the modification cases generated upon modification of solutions to problems, correlating the searched modification case with the proposed solution obtained by the execution unit, and modifying the proposed solution obtained by the execution uni

Abstract: A robot is controlled to move from a predetermined rest point to contact a moving target. The control parameters of the robot are not known. Control is effectuated by predetermining the time required for the robot to move from a rest position to each of a plurality of points within the region in which the target is expected to be found. When the target is identified, its location near the predetermined points at a future time is computed. The known time required from motion of the robot from the rest position to predetermined points adjacent the future location of the target is determined by reference to stored information. The exact time required for the motion may be interpolated between the predetermined points. The time for robot motion is subtracted from the future time to determine the time at which robot motion begins. In a particular embodiment of the invention, a robot coacts with a circular conveyor belt to retrieve objects from the conveyor and transport them to a dump point.

Abstract: In a fuzzy control apparatus, characteristic data which identify a controlled system are measured, and substantial adjustment or correction of a membership function, which includes adjustment of tuning parameters, is performed automatically based on the characteristic data. As a result, the load upon the operator at the time of adjustment is alleviated and it is possible to readily deal with various controlled systems. The invention therefore excels in universality.

Abstract: A SCSI bus controller which has a separate data path from the SCSI bus to the host bus and a separate command path for use to communicate with a local microprocessor. The local microprocessor is connected to a dual port RAM, the other port of which is connected to a bus master controller linked to the host system. Commands and status are passed via the dual port RAM. Data is passed through a FIFO. The local microprocessor does not have access to the data path but only controls direction of the data flow, the initiation of the sequence and the completion of the sequence.

Abstract: A slot accessing method in an object-oriented expert system, wherein data, which is indicative of necessity or non-necessity of re-computation of a slot value and which is created according to a dynamic dependency between a reference slot and a reference slot, is set in a reference slot of an object having a reference rule. When the re-computation is necessary, a flat "T" indicative of the effect is set, whereas when the re-computation is unnecessary, a flat "NIL" indicative of the effect is set. When the value of a slot of an object having a reference slot as its slot value is changed, it is judged whether or not it is necessary to re-compute the slot value of the corresponding reference slot on the basis of data that is indicative of necessity or non-necessity of re-computation of the slot value and that is set in the corresponding reference slot. If the flag "NIL" is set in the corresponding reference slot, then no re-computation is carried out for the slot value.

Abstract: One form of the present invention is a method for identifying interrelations of a plurality of modules. The method includes the steps of identifying one of the plurality of modules as a start module; assigning the start module a link code for a calling module; creating a first entry listing the link code; searching the calling module for a load/call command; designating a module referenced by a load/call command as a called module; creating link code for the called module; and creating an entry listing the link code and the called module.

Abstract: As a step in finding the one most likely word sequence in a spoken language system, an N-best search is conducted to find the N most likely sentence hypotheses. During the search, word theories are distinguished based only on the one previous word. At each state within a word, the total probability is calculated for each of a few previous words. At the end of each word, the probability score is recorded for each previous word theory, together with the name of the previous word. At the end of the sentence, a recursive traceback is performed to derive the list of the N best sentences.

Abstract: A knowledge processing system and a method for operating same for interacting with a user of the system. The system includes a user interface for prompting the user to enter information and for receiving entered information from the user. The user interface is coupled during use to a knowledge model processor (10) that includes a Dialogue Control Interpreter (16) that provides structured messages to a user so as to elicit responses from the user concerning Imperatives of the user, Situations of the user, Knowledge known to the user, and Executive Agents known to the user. This information is stored in a User Awarenesses database (18). The Dialogue Control Interpreter operates in accordance with predetermined dialoguing Imperatives (20) to elicit, record, and access user responses in sequences that guide and motivate the user to follow predetermined sequences of thought, based on the recorded User Awarenesses database of Imperatives, Situations, Knowledge, and Executive Agents.

Abstract: A rule-partitioning system for converting at least a portion of a target expert system program to a rule partitioned RETE network for execution on multiple processors, including a rule partitioning portion for assigning different rules of the target expert system program to different partitions on the basis of previously collected processing statistics and on the use of node sharing; and a compiler for converting the target expert system program to the RETE network, wherein the rules of the RETE network are assigned to the multiple processors in accordance with the partition assignments.

Abstract: Each computer system of the computer network according to the present invention has a management information storage portion for storing information with respect to an access authority in accordance with an owner ID and a conversion rule storage portion for storing a rule for converting the formats of a user ID and an access authority. Each computer system adds a machine ID to a user ID and sends the resultant ID to another computer system when a remote access request is issued. In addition, the computer system determines whether or not the formats of the user ID and the access authority being received accord with those of a local computer system when a remote access is accepted. The computer system converts the formats of the user ID and the access authority being received into those of the local computer system in accordance with a predetermined conversion rule when the formats of the local computer system are not matched with those on the remote computer system.

Abstract: A method and apparatus for arbitrating among multiple requested data transfers based on the availability of transfer resources. A request for the control of a resource is transmitted to an arbiter with information regarding the size of data transfer, internal buses and external buses required. The arbiter compares the information with the space remaining in the buffer, internal bus availability and external bus availability. If all the resources are available to complete the request, then the request is granted arbitration and the requested transfer is started. If any of the resources is not available, the arbiter takes the next request for evaluation. A mechanism is also provided for each request to require the arbiter to wait until all the resources are available to prevent the arbiter from taking on the next request.

Abstract: A learning method for a neural network having at least an input neuron layer, an output neuron layer, and a middle neuron layer between the input and output layers. Each of the layers include a plurality of neurons which are coupled to corresponding neurons in adjacent neural layers. The learning method performs a learning function on the neurons of the middle layer on the basis of the respective outputs, or "ignition patterns", of the neurons in the neural layers adjacent to the middle layer. The ignition pattern of neurons in the input layer is decided artificially according to a preferable image pattern to be input. The ignition pattern of neurons in the output layer is decided artificially according to the ignition pattern of the input layer neurons, wherein the ignition pattern of the output layer neurons is predetermined to correspond to a code or pattern preferable for a user.

Abstract: There is described a system and method for use in a processing system of the type including a plurality of processor subsystems, each processor subsystem including a processor, and being coupled together and to a shared memory by a common bus, wherein the system and method permits exclusive execution of critical sections by each of the processors. A lock buffer associated with each of the processors caches the value of the interlock variable and a control section locally tests the stored interlock variable value responsive to an instruction from its processor. If the control section determines that the interlock variable has the available value, it causes the available value of the interlock variable to be conveyed to its associated processor and the busy value to be written to the local lock buffer and over the common bus to the shared memory under a write-through policy and for updating each lock buffer associated with the other processors under a write-update policy.

Abstract: A self-timed bus arbitration and digital data transfer system is provided for a computer network having multiple master and slave devices sharing a digital data bus. Each master device includes a bus arbitration logic circuit having a time delay element. Each master contending for access to the data bus outputs an identifier on signal lines connecting the master devices. After a period of time comprising the slowest master's operational delay, the bus arbitration circuits determine, on a prioritized basis, which particular master shall have access to the data bus at that time. Upon gaining access, the particular master provides a request signal on a control line connecting the master and slave devices and provides an address on an address bus that may be multiplexed with the data bus. After each slave has decoded the address, as determined by the slowest slave's delay, an acknowledge signal is provided on the control line to the particular master so that data transfer may proceed to/from the selected slave.

Abstract: A signal processor, which receives autocorrelation coefficients, provides lattice coefficients in an optimal manner, and allows the use of any number of available parallel processing units. The signal processor may be implemented in a fully parallel or fully sequential manner, or in a "parallel-partitioned" implementation which provides the benefits of parallel processing, manageable hardware complexity, and optimal signal processing for a given number of available processors.

Abstract: The system for accessing a plurality of devices connected in a network by using a system call, said system capable of accessing a device connected with any one of nodes through the network, the system includes a unit for detecting a device requested to be accessed and a node connected with the device through the network, a unit for converting the system call into a protocol at a time when the device to be accessed is connected with a different node from which the access is not issued, a unit for transmitting the protocol from the node to the different node through the network, and a unit for reconverting the protocol transmitted into the system call so that the system call is executed.

Abstract: An interrupt driven peripheral controller for use in an Industry Standard Architecture (ISA) compatible computer provides a system to minimize power consumption as compared to conventional peripheral controllers. The peripheral controller utilizes an internal interrupt controller which responds to inputs from an ISA compatible microprocessor host, a keyboard, a mouse, and other devices connected to the I/O ports of the ISA compatible computer. The interrupt controller provides an interrupt register for the peripheral controller and generates an interrupt any time one or more of the devices controlled by the peripheral controller is activated. The peripheral controller enters a low power consumption mode if no interrupts are detected for a predetermined period of time. When the interrupt controller generates an interrupt, the peripheral controller is activated from it low power mode and services the device or devices which have caused the interrupt.

Abstract: A pipeline circuit adopted for a CPU or a microprocessor in a computer system, computes the effective branch destination address of a conditional branch instruction before or in parallel with the execution of the conditional branch instruction, judges according to a result of the execution of an instruction just before the conditional branch instruction whether or not a branch condition of the conditional branch instruction is met, and, if the branch condition is met, executes the conditional branch instruction while prefetching and decoding an instruction located at the branch destination address.

Abstract: A method is used to perform arbitration between network devices connected to one of a first network segment and a second network segment, where the first network segment is connected to the second network segment by a long interconnection medium over an extended distance. When one or more network devices connected to the first network segment senses the network is free and desires control of the network for a data transfer, each of these network devices will assert a first network control signal. When the first network control signal is first asserted, this marks the beginning of an arbitration period for the first network segment. The first network control signal is forwarded to the second network segment. Upon the second network segment receiving the first network control signal, any arbitration currently in progress upon the second network segment is aborted.

Abstract: An inference system comprising: a knowledge base defined as a set of rules described for a multiplicity of inference objects of one kind; a working memory storage unit including a region for temporarily storing an intermediate hypothesis to be modified and executed based on rules of the knowledge base for each individual inference object; a working memory selecting unit for performing reading and writing by selecting only the objective working memory from the working memory unit; a parameter storage unit containing parameters provided for respective objects, each parameter being needed when applying the rule of the knowledge base; a parameter selecting unit for reading only the objective parameter for the parameter storage unit; and an inference engine for applying the rule corresponding to contents of the objective working memory from the rules of the knowledge base for one inference object by manipulating the working memory selecting unit and the parameter selecting unit as well.