Abstract: A multi-layer perceptron circuit device using integrated configuration which is capable of incorporating self-learning function and which is easily extendable. The device includes: at least one synapse blocks containing: a plurality of synapses for performing weight calculation on input signals to obtain output signals, which are arranged in planar array defined by a first and a second directions; input signal lines for transmitting the input signals to the synapses, arranged along the first direction; and output signal lines for transmitting the output signal from the synapses, arranged along the second direction not identical to the first direction; at least one input neuron blocks containing a plurality of neurons to be connected with the input signal lines; and at least one output neuron blocks containing a plurality of neurons to be connected with the output signal lines.

Abstract: A method of inputting Chinese characters into a computer directly from Mandarin speech which recognizes a series of monosyllables by separately recognizing syllables and Mandarin tones and assembling the recognized parts to recognize the mono-syllable using Hidden Markov Models. The recognized mono-syllable is used by a Markov Chinese Language Model in a Linguistic decoder section to determine the corresponding Chinese character A Mandarin dictation machine which uses the above method, using a speech input device to receive the Mandarin speech and digitizing it so a personal computer can further process that information. A pitch frequency detector, a Voice signal pre-processing unit, a Hidden Markov Model processor, and a training facility are all attached to the personal computer to perform their associated functions of the method above.

Abstract: In a multitasking data processing system, I/O requests to a disk drive are staged in holding queues from which they are transferred to a service queue. Requests in the latter queue are directly serviced on a FIFO basis by a device driver module running on the system. The system maintains a set of holding queues and an associated service queue separately for each physical drive in the system. Holding queues in each set are prioritized in accordance with base priorities of tasks, and I/O requests to disk drives are entered into associated holding queues having priorities corresponding to those of task threads for which such requests are originated. Prioritization of the holding queues, and a starvation advancement process performed to advance "oldest" enqueued requests to higher priority holding queues, causes the requests to be presented to the disk drive in a sequence based in part on respective task priorities and in part on "fairness" servicing of "service starved" requests.

Abstract: An apparatus for use with a host computing system for controlling access to a first data bus which is external of the host computing system and which first data bus is operatively connected with a second data bus internal of the host computing system. The apparatus comprises a local processing unit which is configured substantially the same as the host processing unit and is driven by a separate local program distinct from the host processing program driving the host processing unit. The apparatus further comprises a supplemental processing circuit for processing information, which supplemental processing circuit is responsive to the host processing unit and to the local processing unit to determine whether the host processing unit or the local processing unit has operative access to the first data bus. In its preferred embodiment, the first data bus and the second data bus are operatively connected by a configurable buffer circuit for effecting data bus connection.

Abstract: A circuit configuration and a method for priority selection of interrupts for a microprocessor in an integrated circuit which includes a central processing unit, a central interrupt node connected to the central processing unit, N interrupt sources for presenting interrupt requests to the central processing unit, peripheral interrupt nodes each being connected to a respective one of the N interrupt sources. A common interrupt bus is connected to the peripheral interrupt nodes and to the central interrupt node. The method for priority selection includes activating the interrupt bus in a prioritizing round in accordance with a priority value with a peripheral interrupt node assigned to an interrupt source in the presence of an interrupt request of the interrupt source.

Abstract: A pulse input device has a standard time generator for outputting standard time information by counting a system clock signal; an input circuit for sampling input signal information from a plurality of channels in synchronization with the standard time information at a predetermined period; a memory for storing the input signal information sampled by the input circuit; a command memory for storing a plurality of instruction commands; and a controller for scanning the instruction commands stored in the command memory to successively execute the instruction commands, for repeating the scanning operation of the instruction commands, and for controlling operations of the device.

Abstract: The specification teaches a structured text processing system for use by such people as bank tellers and insurance agents who work at computer controlled work stations connected together in a network of computers. A draft document in the form of a work in progress (WIP) document is disclosed. The WIP document allows the system to efficiently transmit drafts of highly controlled documents such as loan applications and customer letters from one computer to another in the network for approval or additional information without losing control of the standard form text. The standard form text originates as a shell document having defined variables, the text values of which are entered by tellers at work station screens having prompt messages defined by a related shell detail data set. The variable text is stored into a variable response data set. The shell text and the data sets are made part of the WIP document and therefore are available at other computers in the network for use in revising the WIP document.

Abstract: A status word modification device. A serial communications device (11) contains two universal asynchronous receiver transmitters (UARTs) (14, 15). Each UART contains a first in, first out (FIFO) buffer (14a), two status buffers (14b, 14c), and a FIFO control register (14d). If the applications program in the host (10) is an enhanced application program which supports the use of the FIFO buffer (14a), then the program will cause FIFO enablement instructions to be written into the control register (14d). In this case, the interface circuit (22) allows the status words to pass unaltered whenever the host (10) reads the status buffers (14b, 14c). However, if the applications program is a standard applications program which does not support the use of the FIFO buffer (14a), then the program will not write to the control register (14d).

Abstract: A control apparatus of an electrical appliance comprising a sensor for detecting a physical amount; and a fuzzy inferring device for determining the drive condition of a load by fuzzy inference based on a signal outputted from the sensor, and wherein the sensor has at least one normalized membership function to be used by fuzzy inference and achieves a plurality of membership functions which can be expressed by congruent curves by performing a predetermined subtraction or an addition on the signal outputted from the sensor.

Abstract: A system (30) for atomic access to an I/O device with DMA includes a CPU (32) connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). In this system, graphics subsystem (45) is an I/O device, and atomic access to it is required. Command packet interface (44) to the graphics subsystem (45) transfers geometry and graphics context information from main memory (40) to the graphics subsystem (45). For such transfers, an application writes a list of commands to a physically contiguous locked-down memory buffer (47) in its own address space. Since the system (30) has DMA, the buffer (47) resides in the main memory system (40).

Abstract: A system permitting configuring of its total memory space includes a processor, an external operating device having a first address space and a bus coupling said central processing unit and the operating device. A starting address for the total memory space is defined and the operating device calculates its own starting address from the starting address of the total space.

Abstract: A real-time power conservation apparatus and method for portable computers employs a monitor to determine whether a CPU may rest based upon a real-time sampling of the CPU activity level and to activate a hardware selector to carry out the monitor's determination. If the monitor determines the CPU may rest, the hardware selector reduces CPU clock time; if the CPU is to be active, the hardware selector returns the CPU to its previous high speed clock level. Switching back into full operation from its rest state occurs without a user having to request it and without any delay in the operation of the computer while waiting for the computer to return to a "ready" state. Furthermore, the monitor adjusts the performance level of the computer to manage power conservation in response to the real-time sampling of CPU activity. Such adjustments are accomplished within the CPU cycles and do not affect the user's perception of performance and do not affect any system application software executing on the computer.

Abstract: An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors.

Abstract: A sound synthesizer which may be associated with a personal computer and including apparatus for employing the output of a noise generator which is cataloged to provide a multiplicity of waveforms and apparatus for receiving the multiplicity of waveforms and creating therefrom desired sound signals, thus providing a synthesized sound output.

Abstract: The pitch estimation method is improved. Sub-integer resolution pitch values are estimated in making the initial pitch estimate; the sub-integer pitch values are preferably estimated by interpolating intermediate variables between integer values. Pitch regions are used to reduce the amount of computation required in making the initial pitch estimate. Pitch-dependent resolution is used in making the initial pitch estimate, with higher resolution being used for smaller values of pitch. The accuracy of the voiced/unvoiced decision is improved by making the decision dependent on the energy of the current segment relative to the energy of recent prior segments; if the relative energy is low, the current segment favors an unvoiced decision; if high, it favors a voiced decision.

Abstract: An artificial neural network is provided using a digital architecture having feedforward and feedback processors interconnected with a digital computation ring or data bus to handle complex neural feedback arrangements. The feedforward processor receives a sequence of digital input signals and multiplies each by a weight in a predetermined manner and stores the results in an accumulator. The accumulated values may be shifted around the computation ring and read from a tap point thereof, or reprocessed through the feedback processor with predetermined scaling factors and combined with the feedforward outcomes for providing various types neural network feedback computations. Alternately, the feedforward outcomes may be placed sequentially on a data bus for feedback processing through the network.

Abstract: The subject device manages the access to message queues in a memory (6) by an enqueuer 2 and a dequeuer 7 when the enqueuer has priority over the dequeuer. It solves the contention problem raised when the dequeuer dequeues the last message from a queue while the enqueuer is enqueuing anew one. A queue control block QCB and queue status bits E, A, D are assigned to each queue and stored in memories 20 and 22. Each time dequeuer 7 performs a dequeuing operation it sets its D bit (dequeuer active) before updating the queue head field in the QCB block. When the enqueuer performs an enqueuing operation it sets an abort bit A, if it finds the D bit active and E bit active indicating that the queue contains at least one message to warn the dequeuer that it has to abort its process if it is dequeuing the last message from the queue.

Abstract: A multiprocessor control system which has at least one main storage unit, a plurality of main storage control units, a plurality of processing units, and a control bus. Each processing unit is connected to the main storage unit through one of the main storage control units. When each processing unit transmits a request for access to at least one main storage unit, the processing units transmit the request to the main storage control units to which each processing unit is connected, and simultaneously, to all of the other main storage control units, through the control bus. All of the main storage control units process the request from the processing unit, synchronously, and execute a busy check control or the like. Data transmitted between each processing unit and an arbitrary one of the main storage units is transmitted only through the main storage control unit to which the processing unit is connected.

Abstract: A method and apparatus for training neural networks using evolutionary programming. A network is adjusted to operate in a weighted configuration defined by a set of weight values and a plurality of training patterns are input to the network to generate evaluations of the training patterns as network outputs. Each evaluation is compared to a desired output to obtain a corresponding error. From all of the errors, an overall error value corresponding to the set of weight values is determined. The above steps are repeated with different weighted configurations to obtain a plurality of overall error values. Then, for each set of weight values, a score is determined by selecting error comparison values from a predetermined variable probability distribution and comparing them to the corresponding overall error value. A predetermined number of the sets of weight values determined to have the best scores are selected and copies are made.

Abstract: A mass data storage unit includes a plurality of first data storage modules that form a mass information storage library, a data directory archive for maintaining a directory of the information contained on each data storage module, and data record/playback modules for receiving any selected data storage module in the mass storage library. A plurality of interface computers are coupled to a plurality of host computers for receiving data and for generating request signals to access information stored in the mass storage library. A file directory is coupled to the interface computers and the data directory archive for receiving the request signals, locating in the data directory archive the address containing the stored information and generating a data address location output signal for the stored information.