Abstract: An interface circuit for use between a radio control transmitter equipped with joysticks and a standard data bus of a personal type computer. The interface circuitry includes a microcontroller operated as a reformatter for signals received from the remote control transmitter and a number of integrated circuit latch and buffer circuits connected between the output of the microcontroller and the data bus of a computer to convert the signals output from the microcontroller to the data bus on a direct basis.

Abstract: A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a mode control data written in a mode control register by a processor.

Abstract: A variable length cache system keeps track of the amount of available space on an output device. The capacity of the cache system is continuously increased so long as it is less than the available output space on the output unit. Once the size of the cache system exceeds the available output space on the output unit, which is less than the total space available on the output unit by a predetermined amount, the contents of the cache memory are flushed or written to the output device and the size of the cache memory is reduced to zero.

Abstract: A processor capable of processing a variable word length instruction has a program counter controlled to indicate the head of an instruction by the value of the program counter. There are provided an adder for summing the length of decoded portions in the variable word length instruction in accordance with the progress of the instruction decoding, and another adder for adding the length of the decoded instruction portions to the program counter so as to update the program counter. Further, there is provided a circuit for calculating an operand effective address by using the value of the program counter in the course of the variable word length instruction decoding. Thus, the updating of the program counter and the generation of the effective address are concurrently executed.

Abstract: A method of bit rate de-adaption between an adapted data rate and a user data rate using the ECMA 102 protocol. The user data is transmitted from a data adapter to a user terminal at a first data rate, the adapted data is received by the data adapter at a second data rate, and the second data rate is greater than the first data rate. The adapted data contains a start element and a plurality of data elements while the user data contains a start element and at least one stop element.

Abstract: A case-based retrieval system and method for using same for retrieving justifiably relevant cases from a case library in which past problem solving experiences (cases) are stored. The system obtains the symptoms of a new problem. A set of cases are initially retrieved from the case library based on the symptoms of the new problem. It is then determined for each initially retrieved case using a casual explanation for the case whether the case is justifiably relevant to the new problem, with only justifiably relevant cases being returned to the user of the system.

Abstract: Inference management to estimate conflicting strategies for automatic presentation of a reliable strategy.

Abstract: The present invention is a method for a microprocessor such that when a call is made to a subroutine or an interrupt, a return address is stored in a "stack" memory (RAM) and also that a particular piece of hardware write the return address to an additional register (latches) within the microprocessor. The method enables a comparison to be made at the end of the subroutine or interrupt such that the address to which the subroutine tries to return is compared to the address as latched into the hardware portion of the microprocessor to detect whether any human error has occurred in the programming of the interrupt program or the subroutine.

Abstract: A rule invocation mechanism in an inductive learning engine employing symbolic rules for characterizing a sequence of time-related events. The rules to be tested as hypotheses against new events in the sequence are ranked according to their information content or "quality" value. The efficiency of the rule-to-event pattern matching process for characterizing the new events is increased by not testing a hypothesis if a much better hypothesis already exists. Those hypotheses that characterize events in the sequence are tagged to the event.

Abstract: In a digital computer, there is provided a method of recognizing speech, comprising the steps of: entering a cohesive speech segment; determining gross acoustic attributes of the entered segment; determining fine acoustic attributes of the entered segment; assigning at least one subsyllable to the entered segment based on the gross and fine acoustic attributes determined; repeating the foregoing steps on successive cohesive speech segments to generate at least one sequence of subsyllables; converting the sequence of subsyllables into a sequence of syllables by finding the sequence of subsyllables in a table in which predetermined subsyllable sequences correspond with respective syllables and syllable sequences; combining the converted sequence of syllables into words; and verifying the conformance of the words to a first predetermined set of grammatical rules. An apparatus implementing the method is also disclosed.

Abstract: A number of stand-alone devices are connected in a sequence in a predetermined order for reading information from a bus. The devices read information from the bus one at a time and in the predetermined order in response to a signal.

Abstract: A means and method for training an electronic network of analog cells. A generic universal programmer interface (GUPI) is provided to enable connection of an adaptor to a host computer via a personal computer personal programmer (PCPP) for training an ETANN chip. An opening in the top of the GUPI provides for installation of the adaptor. The adaptor of the present invention plugs into the GUPI module to provide for connecting either an ETANN chip or a Confidence Test Module (CTM) for access by the user via the host computer. A target socket located on the top surface of the adaptor allows the user to physically connect the ETANN chip or the CTM to adapter of the present invention.

Abstract: A method and apparatus are provided for identifying one or more boundaries of a speech pattern within an input utterance. One or more anchor patterns are defined, and an input utterance is received. An anchor section of the input utterance is identified as corresponding to at least one of the anchor patterns. A boundary of the speech pattern is defined based upon the anchor section. Also provided are a method and apparatus for identifying a speech pattern within an input utterance. One or more segment patterns are defined, and an input utterance is received. Portions of the input utterance which correspond to the segment patterns are identified. One or more of the segments of the input utterance are defined responsive to the identified portions.

Abstract: A data processing method and apparatus have a resume function and use a password. When a power switch of a data processing system is turned on while it is selected that the resume function is to be enabled and the password is to be collated, the data processing system displays a message prompting an operator to input a password. When a predetermined password is input from a keyboard or the like, the data processing system executes resume processing, i.e., executes data processing to be continued to data processing executed immediately before the power switch was turned off. When the predetermined password is not input, the resume operation is inhibited, and a content saved by the resume function can be prevented from being disclosed to or destroyed by a third party.

Abstract: A speech system recognizes words from a spoken phrase that conform to checksum constraints. Grammar rules are applied to hypothesize words according to the checksum constraints. The checksum associated with the phrase is thus inherent in the grammar. Sentences which do not meet a predetermined checksum constraint are not valid under the grammar rules and are therefore inherently rejected. The checksum constraints result in increased recognition accuracy.

Abstract: A multi-microcomputer system comprising a first microcomputer system, a second microcomputer system, and a direct memory access controller which has a function of controlling a data transfer operation that is executed between the first microcomputer system and the second microcomputer system.

Abstract: A neural plane, which can form the basis of a neural network or a component thereof, is comprised by an optical modulator, an electrical non-linearity circuit and an optical detector interconnected whereby in use the non-linearity circuit controls the modulator in dependence on the detector output. There are parallel arrays (10, 11, 12) of such modulators, non-linearity circuits and detectors (M, T, D, 30, 33, 34). The modulator, non-linearity circuits and detectors have components formed in a common semiconductor substrate (20), for example by VLSI techniques with a silicon substrate, the modulators (30) may be comprised by liquid crystal on silicon in that case (FIGS. 4, 7).

Abstract: An optical computer for performing product and/or sum operations on input vector information and matrix information includes an array of light emitting elements, the array having a plurality of columns and a plurality of rows. Input circuitry is provided for supplying input vector information to the array while matrix circuitry is provided for dynamically applying matrix information to the array. Logic circuitry is provided for performing one of a logical product and a logical sum operation on the input vector information and the matrix information and for generating an output thereof.

Abstract: A neural net architecture provides for the recognition of an input signal which is a rate variant of a learned signal pattern, reducing the neural net training requirements. The duration of a digital sampling of the input signal is scaled by a time-scaling network, creating a multiplicity of scaled signals which are then compared to memorized signal patterns contained in a self-organizing feature map. The feature map outputs values which indicate how well the scaled input signals match various learned signal patterns. A comparator determines which one of the values is greatest, thus indicating a best match between the input signal and one of the learned signal patterns.

Abstract: There is disclosed a low-power consuming information processing apparatus having a storage unit for storing an application program of a main task, a main CPU capable of operating at a high speed for executing the application program, a sub-CPU for executing a process other than the main task, the sub-CPU being of a low-voltage, low-power consuming type, and a peripheral circuit being controlled by the sub-CPU.