Abstract: This disclosure describes supporting distributed graphics and compute engines in a multi-dielet processor, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronization in such architectures. Each multi-dielet processor includes a hardware-implemented remapping capability and/or a hardware-implemented memory barrier capability.

Abstract: An audience measurement computing system for monitoring a media presentation device in a monitored environment is described and includes a network interface, at least one processor, and a non-transitory computer-readable medium comprising instructions executable by the processor(s). The computing system is configured to obtain, via a cable connected to an input port of the media presentation device, a voltage signal generated by the media presentation device based on an operational state of the media presentation device; compare voltage indicated by the voltage signal to a threshold; based on the comparing, generate timestamped operational state data comprising a record indicative of when the media presentation device is in an on-state; obtain audience measurement data representing one or more media signals communicated to the media presentation device; and transmit, via the network interface over a network and to a central facility, the timestamped operational state data and the audience measurement data.

Abstract: A memory device includes a current mirror coupled to an external resistor, wherein the current mirror is configured to provide a voltage having magnitude based on a resistance of the external resistor, and an oscillator configured to generate a clock signal having a frequency based on the voltage provided from the current mirror. The memory device further includes a counter configured to receive the clock signal and an identifier generation operation enable signal. In response to the identifier generation operation enable signal, counter is configured to provide a count value that adjust in response to the frequency of the clock signal, wherein the count value is used to assign a unique identifier for communication on a to memory module management control bus.

Abstract: An interrupt reception unit receives an interrupt request. In response to a received interrupt request, an interrupt processing unit performs an interrupt process of a first priority or an interrupt process of a second priority having a lower priority than the first priority. An interrupt suppression control unit controls the number of interrupt processes of the second priority processed by the interrupt processing unit in a cycle time according to a suppression condition. The suppression condition is set on the basis of a cycle in which the interrupt process of the second priority occurs and the total number of the interrupt processes of the second priority occurring within a period corresponding to the cycle.

Abstract: Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand.

Abstract: In an embodiment, a computer system comprises one or more co-packaged integrated circuits having a communication fabric that couples various agent circuits. The agent circuits transmit packets via the communication fabric, which can include command-data packets and command packets. In various embodiments, the communication fabric includes an arbitration circuit to arbitrate among packets to transmit on the fabric. The command-data packets may be allocated to a first plurality of virtual channels while the command packets are allocated to a second plurality of virtual channels. The arbitration circuit may arbitrate among the first plurality of virtual channels to select a command-data packet and the second plurality of virtual channels to select a command packet. The arbitration circuit may then arbitrate between the selected command-data packet and the selected command packet to select a winning packet to transmit based on a history of previously selected packets.

Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes memories that store data received from a host device. The memory device includes a memory interface to the host device. The memory device further includes one or more processing devices to perform, using a portion of the data stored in one or more of the memories, computations for a neural network. An output of the neural network is stored in one of the memories. The memory device has a controller that controls memory access by the host device and the processing devices to avoid a conflict. The memory device communicates with the host device over the memory interface using a DRAM bus protocol. This communication includes sending the output of the neural network to the host device.

Abstract: A storage device includes a storage controller, a Flash Memory and a hardware accelerator communicatively coupled. The hardware accelerator is configured to selectively retrieve data stored in the flash memory in response to a request for the data and may perform other operation to accelerate data access for a computer system.

Abstract: Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication units. The first multiplication unit includes first multiply circuitry including a first set of outputs; and first multiplexing logic coupled to the first set of outputs and configured to generate a first partial sum and a first partial carry. The second multiplication unit includes second multiply circuitry including a second set of outputs; and second multiplexing logic coupled to the second set of outputs and configured to generate a second partial sum and a first partial carry.

Abstract: A processing system includes one or more DMA engines that load data from memory or another cache location without storing the data after loading it. As the data propagates past caches located between the memory or other cache location that stores the requested data (“intermediate caches”), the data is selectively copied to the intermediate caches based on a cache replacement policy. Rather than the DMA engine manually storing the data into the intermediate caches, the cache replacement policies of the intermediate caches determine whether the data is copied into each respective cache and a replacement priority of the data. By bypassing storing the data, the DMA engine effectuates prefetching to the intermediate caches without expending unnecessary bandwidth or searching for a memory location to store the data, thus reducing latency and saving energy.

Abstract: A computer-implemented method of performing an operation on an array of values at a processing unit so as to perform a phase of the operation. For each of one or more one-dimensional sequences of values of the array of values a respective section of values of the one-dimensional sequence of values is assigned to each of a plurality of threads, and a first thread of the plurality of threads determines at least one contribution, from the section of values assigned to the first thread, to the phase of the operation that is to be completed by a second thread of the plurality of threads for a neighbouring section of values of the one-dimensional sequence of values. The at least one contribution is written to a memory, and a second thread of the plurality of threads reads the at least one contribution from the memory.

Abstract: The present application relates to a dynamic self-adaptive virtual channel mapping method and apparatus, and a storage medium. The method includes: monitoring equivalent data flows of transaction layer packets of different transmit classes, and obtaining the sum of the equivalent data flows of all the transmit classes, the equivalent data flow being the product of a data length of the transaction layer packet and a coefficient; obtaining a pre-calculation value of the number of virtual channels corresponding to each transmit class base on the sum of the equivalent data flows of the transmit classes; and adjusting mapping from the transmit classes to the virtual channels according to the pre-calculation value to obtain a mapping relationship table from the transmit classes to the virtual channels.

Abstract: There is provided a data processing apparatus and a method of operating a data processing apparatus. The data processing apparatus comprises a plurality of processing elements connected via a network on a single chip arranged to form a triggered spatial architecture. Each processing element comprises front end circuitry configured to generate triggered instructions which are passed to decode circuitry to cause the processing element to perform processing operations. Some processing elements are configured to operate in a producing mode in which the processing element transmits the triggered instructions as consumer instructions to be executed by each of a set of processing elements when operating in a consuming mode. Some processing elements are configured to operate in the consuming mode in which the processing elements retrieve consumer instructions transmitted from a processing element operating in a producing mode, and pass the consumer instructions to the decode circuitry.

Abstract: Computing systems and associated methods are described for managing error conditions associated with shared resources in a partitioned computing system. In some examples, a flush signal is generated by a controller of an expansion card or other component of the partitioned computing system responsive to detecting a communication issue between the component and a first host partition. Responsive to the flush signal, an Input/Output (I/O) fabric of the component terminates active memory transactions for the first host partition and transmits a success status signal associated with the active memory transactions to an initiator of the active memory transactions. The controller may then reset a port coupled to the first host partition to prepare the component for re-establishing a link with the first host partition.

Abstract: A mainboard includes a plurality of interfaces, a first interface of the plurality of interfaces is configured to be connected to the processor board card having a processor circuit, a second interface of the plurality of interfaces is configured to be connected to a non-processor board card, and the first interface and the second interface are connected to each other via a communication circuit; for the mainboard, a connection-centric design idea is adopted, the processor board card is regarded to have the same status as the non-processor board card; because no processor circuit is provided, and only the first interface connected to the processor board card needs to be provided, compared with an original mainboard, an area of the board card in the present application is reduced, and the processor board card and other non-processor board cards may be connected to the mainboard in a stacked manner.

Abstract: The present disclosure provides for a converged compute platform architecture, including a first infrastructure processing unit (IPU)-only configuration and a second configuration wherein the IPU is coupled to a central processing unit, such as an x86 processor. Connectivity between the two configurations may be accomplished with a PCIe switch, or the two configurations may communicate through remote direct memory access (RDMA) techniques. Both configurations may use ML acceleration through a single converged architecture.

Abstract: Apparatuses, systems, and techniques to execute software programs. In at least one embodiment, an application programming interface (API) is performed to cause an indication to be stored of whether one or more memory operations to be performed are dependent on one or more other memory operations.

Abstract: A microcontroller system that includes a central processing unit (CPU), a first system memory, a first peripheral module, and a DMA controller is disclosed. The DMA controller includes a DMA processor, a DMA memory, and a DMA interconnect. The DMA memory stores information associated with the DMA processor. The DMA processor receives a command from the CPU or a signal from a peripheral processor of the first peripheral module that a first data transfer is requested. The DMA processor receives first data from the first system memory or the first peripheral module. The DMA processor, based at least in part on the information stored in the DMA memory, transmits the first data to the first peripheral module or the first system memory, thereby sparing the CPU from managing the transferring of the first data.

Abstract: The disclosed device includes a heterogeneous processor architecture having heterogeneous processors, and a control circuit that can assign, in response to an interrupt, the interrupt to one of the heterogenous processors that is selected based on power efficiency. Various other methods, systems, and computer-readable media are also disclosed.