Patents Examined by Michael Sun
  • Patent number: 11449443
    Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 20, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Oleg Kragel, Xiangyu Tang, Vijay Sivasankaran, Mikhail Palityka
  • Patent number: 11443479
    Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: September 13, 2022
    Assignee: Apple Inc.
    Inventors: Winnie W. Yeung, Leela Kishore Kothamasu, Zelin Zhang, Guanlan Xu, Eddie M. Robinson
  • Patent number: 11436168
    Abstract: An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: September 6, 2022
    Assignees: Samsung Electronics Co., Ltd., SNU R&DB FOUNDATION
    Inventors: Seung Wook Lee, Hweesoo Kim, Jung Ho Ahn
  • Patent number: 11429545
    Abstract: The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed in a host side to include: obtaining a value of an extended device-specific data (Ext_CSD) register in a flash controller from the flash controller, where the host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol; and allocating space in a system memory as an HPA buffer, and storing a plurality of first logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller when the value of the Ext_CSD register comprises information indicating that an HPA function is supported, where each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: August 30, 2022
    Assignee: SILICON MOTION, INC.
    Inventor: Po-Yi Shih
  • Patent number: 11429444
    Abstract: Examples relate to managing distribution of a total number of I/O queue pairs of an NVMe target among a plurality of NVM subsystems of the NVMe target and a plurality of hosts connected to the NVMe target. A target controller of the NVMe target defines a number of I/O queue pairs for a dedicated pool and a number of I/O queue pairs for a reserved pool based on the total number of I/O queue pairs. The target controller distributes a number of I/O queue pairs to each of the hosts from the number of I/O queue pairs of the dedicated pool and utilizes the number of I/O queue pairs of the reserved pool to balance out the number of I/O queue pairs on each of the hosts by selectively changing the number of I/O queue pairs of the reserved pool.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: August 30, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kumar Rahul, Krishna Babu Puttagunta, Alice Terumi Clark, Barry A. Maskas, Rupin Tashi Mohan
  • Patent number: 11422820
    Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11409575
    Abstract: The present disclosure provides a computation method and product thereof. The computation method adopts a fusion method to perform machine learning computations. Technical effects of the present disclosure include fewer computations and less power consumption.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 9, 2022
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD
    Inventors: Shaoli Liu, Yuzhe Luo
  • Patent number: 11409675
    Abstract: A data transmission method for a convolution operation, and a convolution operation apparatus including a fetcher that includes a loader, at least one sender, a buffer controller, and a reuse buffer. The method includes loading, by the loader, input data of an input feature map according to a loading order, based on input data stored in the reuse buffer, a shape of a kernel to be used for a convolution operation, and two-dimensional (2D) zero-value information of weights of the kernel; storing, by the buffer controller, the loaded input data in the reuse buffer of an address cyclically assigned according to the loading order; and selecting, by each of the at least one sender, input data corresponding to each output data of a convolution operation among the input data stored in the reuse buffer, based on one-dimensional (1D) zero-value information of the weights, and outputting the selected input data.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: August 9, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunsun Park, Jun-Woo Jang, Yoojin Kim, Channoh Kim
  • Patent number: 11392528
    Abstract: Methods and apparatus for improved data movement operations through interconnect fabric. In one embodiment, Non-Transparent Bridge (NTB) technology used to perform data movement operations between a host and multiple peer devices using a DMA (direct memory access) engine and at least one descriptor ring having enhanced descriptor entries. In one implementation, descriptor ring entries include source and destination address information, address translation information, and fabric partition information. In one implementation, a DMA engine is configured directly access host memory and generate data packets using the descriptor entry information. In one embodiment, the descriptor ring is a virtual descriptor ring located on DMA hardware, host memory, or elsewhere in the NT fabric address space, and may be accessed by user processes.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: July 19, 2022
    Assignee: CIGAIO NETWORKS, INC.
    Inventor: Doug Meyer
  • Patent number: 11379386
    Abstract: Systems and methods are disclosed and include receiving, with a peripheral device, a message packet from a portable device, the message packet including an authenticated packet with a de-whitened tone byte inserted therein. The portable device generates first message authentication code (MAC) bytes based on a shared secret key and generates the authenticated packet based on the first MAC bytes, first nonce bytes, and a message byte. The peripheral device validates the message packet in response to determining that the first MAC bytes match second MAC bytes and that the first nonce bytes match second nonce bytes. The peripheral device generates a reconstructed message packet in response to validating the message packet by removing the de-whitened tone byte from the authenticated packet. The communication gateway establishes a communication link between the portable device and the communication gateway in response to receiving the reconstructed message packet.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: July 5, 2022
    Assignees: DENSO International America, Inc., DENSO CORPORATION
    Inventors: Raymond Michael Stitt, Thomas Peterson, Karl Jager, Kyle Golsch
  • Patent number: 11379388
    Abstract: A memory controller includes an address decoder, a first command queue coupled to a first output of the address decoder for receiving memory access requests for a first memory channel, and the second command queue coupled to a second output of the address decoder for receiving memory access requests for a second memory channel. A request credit control circuit is coupled to the first command queue and the second command queue, and operates to track a number of outstanding request credits. The request credit control circuit issues a request credit in response to a designated event based on a number of available entries of the first and second command queues.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: July 5, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, Shriram Ravichandran
  • Patent number: 11372645
    Abstract: Deferred command execution by a command processor (CP) may be performed based on a determination that at least one command of a primary buffer is located between a first link of the primary buffer and a second link of the primary buffer. The first link and the second link may be to one or more secondary buffers that includes a set of commands. The CP may initiate, before executing, a fetch of a first set of commands in the set of commands based on the first link, a fetch of the at least one command of the primary buffer, and a fetch of a second set of commands in the set of commands based on the second link. After initiating the fetch of the second set of commands, the CP may execute the first set of commands, the at least one command of the primary buffer, and the second set of commands.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 28, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Nigel Poole, Joohi Mittal
  • Patent number: 11372648
    Abstract: A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11360803
    Abstract: Method and systems for executing a non-maskable interrupt are provided. In one aspect, a method for executing a non-maskable interrupt includes: obtaining an interrupt request in a non-secure mode, and interrupting an operation of an operating system (OS); saving, in a secure mode, a status of the OS when the operation of the OS is interrupted; executing, in the non-secure mode, a procedure defined for the interrupt request; resume, in the secure mode, the status of the OS; and after resuming the status of the OS, continue executing the operation of the OS in the non-secure mode.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: June 14, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jun Ma, Tianhong Ding, Zhaozhe Tong
  • Patent number: 11360818
    Abstract: A method for data management is provided. The method comprises: storing the plurality of items in a contiguous space within the memory, executing an instruction containing an address and a size that together identify the contiguous space to transmit the plurality of items from the main memory to a random-access memory (RAM) on a chip, and the chip includes a computing unit comprising a plurality of multipliers; and instructing the computing unit on the chip to: retrieve multiple of the plurality of items from the RAM; and perform a plurality of parallel operations using the plurality of multipliers with the multiple items to yield output data.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 14, 2022
    Assignee: BEIJING HORIZON INFORMATION TECHNOLOGY CO., LTD
    Inventors: Chang Huang, Liang Chen, Kun Ling, Feng Zhou
  • Patent number: 11360777
    Abstract: A cache system, having a first cache, a second cache, and a logic circuit coupled to control the first cache and the second cache according to an execution type of a processor. When an execution type of a processor is a first type indicating non-speculative execution of instructions and the first cache is configured to service commands from a command bus for accessing a memory system, the logic circuit is configured to copy a portion of content cached in the first cache to the second cache. The cache system can include a configurable data bit. The logic circuit can be coupled to control the caches according to the bit. Alternatively, the caches can include cache sets. The caches can also include registers associated with the cache sets respectively. The logic circuit can be coupled to control the cache sets according to the registers.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11347662
    Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Ishwar Agarwal, Rupin H. Vakharwala, Rajesh M. Sankaran, Stephen R. Van Doren
  • Patent number: 11341069
    Abstract: A method of operating a processing unit includes storing a first copy of a first interrupt control value in a cache device of the processing unit, receiving from an interrupt controller a first interrupt message transmitted via an interconnect fabric, where the first interrupt message includes a second copy of the first interrupt control value, and if the first copy matches the second copy, servicing an interrupt specified in the first interrupt message.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: May 24, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bryan P Broussard, Paul Moyer, Eric Christopher Morton, Pravesh Gupta
  • Patent number: 11327909
    Abstract: In one embodiment, data communication apparatus includes a network interface including one or more ports for connection to a packet data network and configured to receive content transfer requests from at least one remote device over the network, a storage sub-system to be connected to local peripheral storage devices, and including at least one peripheral interface, and a memory sub-system including a cache and RAM, and processing circuitry to manage transfer of content between the remote device(s) and the local peripheral storage devices via the peripheral interface(s) and the cache, responsively to the content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to a metric of the storage sub-system so that while ones of the content transfer requests are being served, other ones of the content transfer requests pending serving are queued in at least one pending queue.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 10, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Eliav Bar-Ilan, Oren Duer, Amir Ancel, Yossi Kendel, Idan Burstein
  • Patent number: 11321126
    Abstract: Disclosed herein is a multiprocessor system for facilitating real-time multitasking processing. The multiprocessor system may include a task scheduler and a plurality of processors. Further, the task scheduler may be configured for receiving an event associated with the multiprocessor system, evaluating a plurality of task priorities associated with a plurality of tasks based on the event, determining a plurality of new task priorities for the plurality of tasks and assigning the plurality of tasks to a plurality of lists based on the determining. Further, the plurality of processors may be communicatively coupled with the task scheduler. Further, the plurality of processors serves the plurality of lists. Further, a processor of the plurality of processors may be configured for processing the plurality of tasks assigned to a list of the plurality of lists based on the plurality of new task priorities.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 3, 2022
    Inventor: Ricardo Luis Cayssials