Abstract: A communication system is configured to be capable of executing an address assignment process including: a first process for detecting presence/absence of an identification current input by means of an identification current detection unit when a constant current supply has generated an identification current output with a switch and a second transistor in an off state; and a second process for repeatedly executing the first process while, with respect to a slave among the slaves that has had the identification current input detected therein, stopping generation of the identification current output thereafter, and assigning an address to a single slave among the slaves that has not had the identification current input detected therein, and is also configured to be capable of executing the address assignment process while excluding a slave among the slaves that has had the address assigned thereto.

Abstract: Various embodiments of the teachings herein include a container runtime environment comprising: container application instances; and container monitoring instances. The container monitoring instances monitor the container application instances. Monitoring of the container application instances includes subdivided monitoring tasks. Each monitoring task is assigned at least one privilege exclusively enabling an execution of the respective assigned monitoring task. Execution of the monitoring task comprises enforcement of an assigned set of rules. The container monitoring instances are each allocated a monitoring task. The container monitoring instances each have the at least one privilege assigned to their monitoring task.

Abstract: A reservation station design method for vector execution units includes: S1, receiving an instruction by a reservation station, decoding the number of ticks for executing the instruction, and extracting an address of each source operand; S2, determining whether each source operand is ready; selecting a specific instruction slot to store the instruction, monitoring a bypass path, and pulling up a status bit of each not-ready source operand; S3, sorting non-transmitted instructions, determining a specific instruction according to a sorting result, and transmitting the specific instruction to a vector execution unit, and sending out a prewrite-back signal; and S4, setting hold signals, and blocking an instruction to be blocked; and when the address of each source operand corresponding to any one non-transmitted instruction is identical with an address in the prewrite-back signal, counting ticks, and in the last tick, transmitting a corresponding non-transmitted instruction to the vector execution unit for execut

Abstract: The present application discloses a computing-in-memory circuit, chip and electronic device, wherein the computing-in-memory circuit comprises: a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit; the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to the N resistive random access memories selected of the resistive random access memory array, wherein N is an integer and N?2; the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on the N-way currents output from the N resistive random access memories selected; the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

Abstract: Techniques can include: thread TH1 acquiring a spinlock; while TH1 holds the spinlock, adding threads TH2 and TH3 to a wait queue based on a FIFO (first in first out) ordering in which threads attempt to acquire the spinlock, where TH1, TH2 and TH3 respectively have positions P1, P2 and P3 in the FIFO ordering; while TH1 holds the spinlock, pre-empting TH2; while TH2 is inactive and waiting at P2 in the FIFO ordering of the queue, TH1 releasing the spinlock; detecting that the spinlock is free and that TH3 is waiting in the queue at P3, where TH2 is next, in the FIFO ordering of threads in the queue, to acquire the spinlock after released by TH1; and responsive to said detecting, performing first processing including: cancelling the second position or index P2 of TH2 in the FIFO ordering; and TH3 acquiring the spinlock.

Abstract: A storage device includes a memory controller, a buffer memory, and a memory device including a plurality of non-volatile memory devices connected to the memory controller via an identical channel. The memory controller is configured to generate a first command for performing a first DMA operation and a second command for performing a second DMA operation, adjust an output time interval between a first output time point of the first command with respect to a first non-volatile memory device among the plurality of non-volatile memory devices and a second output time point of the second command with respect to a second non-volatile memory device among the plurality of non-volatile memory devices, and is configured to add a time interval corresponding to the output time interval between an end time point of the first DMA operation corresponding to the first command and a start time point of the second DMA operation corresponding to the second command.

Abstract: A computing system includes a host device and an acceleration device. The host device is in a communication connection with the acceleration device. The host device is configured to send invocation information to the acceleration device. The invocation information indicates a storage address of the first data. The acceleration device is configured to receive the invocation information from the host device, obtain the first data from a memory based on the storage address, and perform the to-be-processed task based on the first data to obtain a processing result. The host device notifies the acceleration device of the storage address, and the acceleration device directly obtains the data from the memory based on the storage address such that the host device is prevented from obtaining the data from the memory.

Abstract: This disclosure describes supporting distributed graphics and compute engines in a multi-dielet processor, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronization in such architectures. Each multi-dielet processor includes a hardware-implemented remapping capability and/or a hardware-implemented memory barrier capability.

Abstract: An audience measurement computing system for monitoring a media presentation device in a monitored environment is described and includes a network interface, at least one processor, and a non-transitory computer-readable medium comprising instructions executable by the processor(s). The computing system is configured to obtain, via a cable connected to an input port of the media presentation device, a voltage signal generated by the media presentation device based on an operational state of the media presentation device; compare voltage indicated by the voltage signal to a threshold; based on the comparing, generate timestamped operational state data comprising a record indicative of when the media presentation device is in an on-state; obtain audience measurement data representing one or more media signals communicated to the media presentation device; and transmit, via the network interface over a network and to a central facility, the timestamped operational state data and the audience measurement data.

Abstract: A memory device includes a current mirror coupled to an external resistor, wherein the current mirror is configured to provide a voltage having magnitude based on a resistance of the external resistor, and an oscillator configured to generate a clock signal having a frequency based on the voltage provided from the current mirror. The memory device further includes a counter configured to receive the clock signal and an identifier generation operation enable signal. In response to the identifier generation operation enable signal, counter is configured to provide a count value that adjust in response to the frequency of the clock signal, wherein the count value is used to assign a unique identifier for communication on a to memory module management control bus.

Abstract: An interrupt reception unit receives an interrupt request. In response to a received interrupt request, an interrupt processing unit performs an interrupt process of a first priority or an interrupt process of a second priority having a lower priority than the first priority. An interrupt suppression control unit controls the number of interrupt processes of the second priority processed by the interrupt processing unit in a cycle time according to a suppression condition. The suppression condition is set on the basis of a cycle in which the interrupt process of the second priority occurs and the total number of the interrupt processes of the second priority occurring within a period corresponding to the cycle.

Abstract: Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand.

Abstract: In an embodiment, a computer system comprises one or more co-packaged integrated circuits having a communication fabric that couples various agent circuits. The agent circuits transmit packets via the communication fabric, which can include command-data packets and command packets. In various embodiments, the communication fabric includes an arbitration circuit to arbitrate among packets to transmit on the fabric. The command-data packets may be allocated to a first plurality of virtual channels while the command packets are allocated to a second plurality of virtual channels. The arbitration circuit may arbitrate among the first plurality of virtual channels to select a command-data packet and the second plurality of virtual channels to select a command packet. The arbitration circuit may then arbitrate between the selected command-data packet and the selected command packet to select a winning packet to transmit based on a history of previously selected packets.

Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.

Abstract: A storage device includes a storage controller, a Flash Memory and a hardware accelerator communicatively coupled. The hardware accelerator is configured to selectively retrieve data stored in the flash memory in response to a request for the data and may perform other operation to accelerate data access for a computer system.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes memories that store data received from a host device. The memory device includes a memory interface to the host device. The memory device further includes one or more processing devices to perform, using a portion of the data stored in one or more of the memories, computations for a neural network. An output of the neural network is stored in one of the memories. The memory device has a controller that controls memory access by the host device and the processing devices to avoid a conflict. The memory device communicates with the host device over the memory interface using a DRAM bus protocol. This communication includes sending the output of the neural network to the host device.

Abstract: Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication units. The first multiplication unit includes first multiply circuitry including a first set of outputs; and first multiplexing logic coupled to the first set of outputs and configured to generate a first partial sum and a first partial carry. The second multiplication unit includes second multiply circuitry including a second set of outputs; and second multiplexing logic coupled to the second set of outputs and configured to generate a second partial sum and a first partial carry.

Abstract: A processing system includes one or more DMA engines that load data from memory or another cache location without storing the data after loading it. As the data propagates past caches located between the memory or other cache location that stores the requested data (“intermediate caches”), the data is selectively copied to the intermediate caches based on a cache replacement policy. Rather than the DMA engine manually storing the data into the intermediate caches, the cache replacement policies of the intermediate caches determine whether the data is copied into each respective cache and a replacement priority of the data. By bypassing storing the data, the DMA engine effectuates prefetching to the intermediate caches without expending unnecessary bandwidth or searching for a memory location to store the data, thus reducing latency and saving energy.

Abstract: A computer-implemented method of performing an operation on an array of values at a processing unit so as to perform a phase of the operation. For each of one or more one-dimensional sequences of values of the array of values a respective section of values of the one-dimensional sequence of values is assigned to each of a plurality of threads, and a first thread of the plurality of threads determines at least one contribution, from the section of values assigned to the first thread, to the phase of the operation that is to be completed by a second thread of the plurality of threads for a neighbouring section of values of the one-dimensional sequence of values. The at least one contribution is written to a memory, and a second thread of the plurality of threads reads the at least one contribution from the memory.

Abstract: The present application relates to a dynamic self-adaptive virtual channel mapping method and apparatus, and a storage medium. The method includes: monitoring equivalent data flows of transaction layer packets of different transmit classes, and obtaining the sum of the equivalent data flows of all the transmit classes, the equivalent data flow being the product of a data length of the transaction layer packet and a coefficient; obtaining a pre-calculation value of the number of virtual channels corresponding to each transmit class base on the sum of the equivalent data flows of the transmit classes; and adjusting mapping from the transmit classes to the virtual channels according to the pre-calculation value to obtain a mapping relationship table from the transmit classes to the virtual channels.