Patents Examined by Michael Sun
  • Patent number: 11835993
    Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: December 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: DongSik Cho, Jeonghoon Kim, Rohitaswa Bhattacharya, Jaeshin Lee, Honggi Jeong
  • Patent number: 11829769
    Abstract: Systems and/or methods can include techniques to exploit dynamic timing slack on the chip. By using a special clock generator, the clock period can be shrunk as needed at every cycle. The clock period is determined during operation by checking “critical path messengers” to indicate how much dynamic timing slack exists. Elastic pipeline timing can also be introduced to redistribute timing among pipeline stages to bring further benefits.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: November 28, 2023
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Jie Gu, Russell E. Joseph
  • Patent number: 11829764
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: November 28, 2023
    Assignee: MIPS Tech, LLC
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
  • Patent number: 11824752
    Abstract: A multi-port data storage device to at least provide port-to-port communication between nodes. The multi-port storage device includes a first port, a second port and a bridge. The first port can be operatively coupled to a first node of a plurality of nodes. The second port can be operatively coupled to a second node of the plurality of nodes. The bridge can receive one or more data packets via the first or second ports to be transmitted to one of the plurality of nodes and to transmit one or more received data packets to another multi-port data storage device, to the first node, or to the second node.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: November 21, 2023
    Assignee: Seagate Technology LLC
    Inventor: Thomas Roy Prohofsky
  • Patent number: 11816485
    Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.
    Type: Grant
    Filed: July 4, 2021
    Date of Patent: November 14, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Kai Chirca, Timothy D. Anderson, Todd T. Hahn, Alan L. Davis
  • Patent number: 11809343
    Abstract: A system includes multiple memory-compute nodes coupled to one another over a scale fabric, where each memory-compute node includes a hybrid threading processor; a memory controller; a fabric interface; and a network on chip (NOC) that provides communication between the hybrid threading processor, the fabric interface, and the memory controller, wherein the fabric interface supports a first virtual channel (VC0), and a second virtual channel (VC1) to the NOC, and supports the first virtual channel (VC0), the second virtual channel (VC1), and a third virtual channel (VC2) to the scale fabric.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 11797461
    Abstract: A data transmission method for a convolution operation, and a convolution operation apparatus including a fetcher that includes a loader, at least one sender, a buffer controller, and a reuse buffer. The method includes loading, by the loader, input data of an input feature map according to a loading order, based on input data stored in the reuse buffer, a shape of a kernel to be used for a convolution operation, and two-dimensional (2D) zero-value information of weights of the kernel; storing, by the buffer controller, the loaded input data in the reuse buffer of an address cyclically assigned according to the loading order; and selecting, by each of the at least one sender, input data corresponding to each output data of a convolution operation among the input data stored in the reuse buffer, based on one-dimensional (1D) zero-value information of the weights, and outputting the selected input data.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: October 24, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunsun Park, Jun-Woo Jang, Yoojin Kim, Channoh Kim
  • Patent number: 11789879
    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyungmin Jin, Jindo Byun, Younghoon Son, Youngdon Choi, Junghwan Choi
  • Patent number: 11782844
    Abstract: A method comprising: receiving, at a vector processor, a request to store data; performing, by the vector processor, one or more transforms on the data; and directly instructing, by the vector processor, one or more storage device to store the data; wherein performing one or more transforms on the data comprises: erasure encoding the data to generate n data fragments configured such that any k of the data fragments are usable to regenerate the data, where k is less than n; and wherein directly instructing one or more storage device to store the data comprises: directly instructing the one or more storage devices to store the plurality of data fragments.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: October 10, 2023
    Assignee: Nyriad Inc.
    Inventors: Xavier Aldren Simmons, Jack Spencer Turpitt, Rafael John Patrick Shuker, Tyler Wilson Hale, Alexander Kingsley St. John, Stuart John Inglis
  • Patent number: 11782709
    Abstract: Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Robert Valentine, Galina Ryvchin, Piotr Majcher, Mark J. Charney, Elmoustapha Ould-Ahmed-Vall, Jesus Corbal, Milind B. Girkar, Zeev Sperber, Simon Rubanovich, Amit Gradstein
  • Patent number: 11775308
    Abstract: A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11762787
    Abstract: A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores. One-half of the memory access channel interfaces are to, in a second mode, each respectively receive memory access commands, directed to a corresponding two of four of the groups of memory cores. The memory access channel interfaces to have electrical connection conductors that lie on opposing sides of at least one line of reflectional symmetry from a second one-half of the one-half of the at least four memory access channel interfaces.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 19, 2023
    Assignee: Rambus Inc.
    Inventors: Steven C. Woo, Torsten Partsch
  • Patent number: 11762788
    Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: September 19, 2023
    Assignee: Netlist, Inc.
    Inventors: Hyun Lee, Jayesh R. Bhakta
  • Patent number: 11756074
    Abstract: An audience measurement computing system for monitoring a media presentation device in a monitored environment is described and includes a network interface, at least one processor, and a non-transitory computer-readable medium comprising instructions executable by the processor(s). The computing system is configured to obtain, via a cable connected to an input port of the media presentation device, a voltage signal generated by the media presentation device based on an operational state of the media presentation device; compare voltage indicated by the voltage signal to a threshold; based on the comparing, generate timestamped operational state data comprising a record indicative of when the media presentation device is in an on-state; obtain audience measurement data representing one or more media signals communicated to the media presentation device; and transmit, via the network interface over a network and to a central facility, the timestamped operational state data and the audience measurement data.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: September 12, 2023
    Assignee: The Nielsen Company (US), LLC
    Inventors: Mark Cave, Joseph Volpatti
  • Patent number: 11755328
    Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: September 12, 2023
    Assignee: Apple Inc.
    Inventors: Aditya Kesiraju, Brett S. Feero, Nikhil Gupta, Viney Gautam
  • Patent number: 11748278
    Abstract: Examples described herein relate to executing a poller to poll for received communications over multiple transport layer protocols from a connection to identify a received communication from one of the multiple transport layer protocols and identify a second received communication from a different one of the multiple transport layer protocols. A change to the different one of the multiple transport layer protocols occurs in response to failure of the one of the multiple transport layer protocols or slow transport rate using the one of the multiple transport layer protocols. In some examples, the poller is executed in user space and transport layer protocol processing of the received communication and second received communication occur in kernel space.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Ziye Yang, Changpeng Liu, Gang Cao, Qun Wan
  • Patent number: 11748280
    Abstract: A coherent data processing system includes a system fabric communicatively coupling a plurality of nodes arranged in a plurality of groups. A plurality of coherence agents are distributed among the nodes and are assigned responsibility for certain addresses. A topology data structure indicates by group and node differing physical locations within the data processing system of the plurality of coherence agents. A master accesses the topology data structure utilizing a request address to obtain a particular group and node of a particular coherence agent uniquely assigned the request address. The master initially issues, on the system fabric, a memory access request specifying the request address and utilizing a remote scope of broadcast that includes the particular node and excludes at least one other node in the particular group, where the particular node is a different one of the plurality of nodes than a home node containing the master.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: September 5, 2023
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Siegel, Guy L. Guthrie
  • Patent number: 11734015
    Abstract: A cache system, having a first cache, a second cache, and a logic circuit coupled to control the first cache and the second cache according to an execution type of a processor. When an execution type of a processor is a first type indicating non-speculative execution of instructions and the first cache is configured to service commands from a command bus for accessing a memory system, the logic circuit is configured to copy a portion of content cached in the first cache to the second cache. The cache system can include a configurable data bit. The logic circuit can be coupled to control the caches according to the bit. Alternatively, the caches can include cache sets. The caches can also include registers associated with the cache sets respectively. The logic circuit can be coupled to control the cache sets according to the registers.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11734194
    Abstract: A method is provided that includes performing, by a processor in response to a dual issue multiply instruction, multiplication of operands of the dual issue multiply instruction using multiplication units comprised in a data path of the processor and configured to operate together to determine a product of the operands, and storing, by the processor, the product in a storage location indicated by the dual issue multiply instruction.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: August 22, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy David Anderson, Mujibur Rahman
  • Patent number: 11734010
    Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto