Patents Examined by Michael Sun
  • Patent number: 11068318
    Abstract: A method for dynamically providing a status of a hardware thread/hardware resource independent of the operation of the hardware thread/hardware resource using an inter-thread communication protocol. A master hardware thread may be configured to communicate status requests to associated slave hardware threads and/or hardware resources. Each slave hardware thread/hardware resource may be configured with hardware logic configured to automatically determine status information for the slave hardware thread/hardware resource and communicate a status response to the master hardware thread without interrupting processing of the slave hardware thread/hardware resource.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • Patent number: 11068273
    Abstract: Swapping and restoring context-specific branch predictor states on context switches in a processor. A branch prediction circuit in an instruction processing circuit of a processor includes a private branch prediction memory configured to store branch prediction states for a context of a process being executed. The branch prediction states are accessed by the branch prediction circuit to predict outcomes of its branch instructions of the process. In certain aspects, when a context switch occurs in the processor, branch prediction states stored in a private branch prediction memory and associated with the current, to-be-swapped-out context, are swapped out of the private branch prediction memory to the shared branch prediction memory. Branch prediction states in the shared branch prediction memory previously stored (i.e., swapped out) and associated with to-be-swapped-in context for execution are restored in the private branch prediction memory to be used for branch prediction.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 20, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rami Mohammad Al Sheikh, Michael Scott McIlvaine
  • Patent number: 11068326
    Abstract: Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 20, 2021
    Assignee: Apple Inc.
    Inventors: Jason McElrath, Karan Sanghi, Saurabh Garg
  • Patent number: 11061681
    Abstract: A method, system, and/or processor for processing data is disclosed that includes processing a parent stream; detecting a branch instruction in the parent stream; activating an additional child stream; setting a copy select vector of the child stream to be the same as the copy select vector of the parent stream; dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, the method further includes setting the copy select bits in the copy select vector for the child stream to equal the copy select bits in the copy select vector for the parent stream. A first parent mapper copy in an embodiment is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q Nguyen, Brian W. Thompto
  • Patent number: 11061848
    Abstract: An information processing apparatus includes: a connection detection unit configured to detect connection of a device to USB connector; a device information acquisition unit configured to acquire first information indicating whether the device detected by the connection detection unit as being connected supports USB-PD standard, second information indicating whether the device supports one or both of power supply and power reception in the case where the device supports the USB-PD standard, and third information indicating whether the device supports data communication by USB; and a device determination unit configured to determine a type of the device based on the first information, the second information, and the third information.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: July 13, 2021
    Assignee: LENOVO (SINGAPORE) PTE. LTD.
    Inventors: Yuichiro Seto, Munefumi Nakata
  • Patent number: 11061841
    Abstract: A method of implementing a multi-threaded device driver for a computer system is disclosed. A polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: July 13, 2021
    Assignee: Rambus, Inc.
    Inventors: Bart Trojanowski, Michael L. Takefman, Maher Amer
  • Patent number: 11055095
    Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: July 6, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Kai Chirca, Timothy D. Anderson, Todd T. Hahn, Alan L. Davis
  • Patent number: 11048650
    Abstract: A method for integrating a processing-in-sensor unit and an in-memory computing includes the following steps. A providing step is performed to transmit the first command signal and the initial data to the in-memory computing unit. A converting step is performed to drive the first command signal and the initial data to convert to a second command signal and a plurality of input data through a synchronizing module. A fetching step is performed to drive a frame difference module to receive the input data to fetch a plurality of difference data. A slicing step is performed to drive a bit-slicing module to receive the difference data and slice each of the difference data into a plurality of bit slices. A controlling step is performed to encode the difference address into a control signal, and the in-memory computing unit accesses each of the bit slices according to the control signal.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 29, 2021
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh, Syuan-Hao Sie
  • Patent number: 11042372
    Abstract: A method to transpose source data in a processor in response to a vector bit transpose instruction includes specifying, in respective fields of the vector bit transpose instruction, a source register containing the source data and a destination register to store transposed data. The method also includes executing the vector bit transpose instruction by interpreting N×N bits of the source data as a two-dimensional array having N rows and N columns, creating transposed source data by transposing the bits by reversing a row index and a column index for each bit, and storing the transposed source data in the destination register.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 22, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph Zbiciak, Dheera Balasubramanian Samudrala, Duc Bui
  • Patent number: 11042376
    Abstract: A method of allocating a virtual register stack (10) of a processing unit in a stack machine is provided. The method comprises allocating a given number of topmost elements (11) of the virtual register stack (10) in a physical register file (17) of the stack machine and allocating subsequent elements of the virtual register stack (10) in a hierarchical register cache (13) of the stack machine.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 22, 2021
    Inventor: Klaus Kinzinger
  • Patent number: 11029954
    Abstract: According to one general aspect, an apparatus may include execution unit circuits, each configured to access one or more pieces of data. The apparatus may include local register file circuits, each associated with a respective execution unit circuit and each configured to store data. The apparatus may include a main register circuit. The main register circuit may include a main register file circuit configured to store data. The main register circuit may include a local index register circuit configured to map an index supplied by the main register file circuit to a storage location in the local register file circuits. The main register circuit may be configured to: receive from a control circuit a request to access the storage location of the specified data, and supply a target local register file circuit with the target local register file circuit's storage location of the specified data.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: June 8, 2021
    Inventors: Wilson Wai Lun Fung, Mrinal Deo
  • Patent number: 11023241
    Abstract: Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 1, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrej Kocev, Jay Fleischman, Kai Troester, Johnny C. Chu, Tim J. Wilkens, Neil Marketkar, Michael W. Long
  • Patent number: 11024583
    Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: June 1, 2021
    Assignee: XILINX, INC.
    Inventors: Austin H. Lesea, Sundararajarao Mohan, Stephen M. Trimberger
  • Patent number: 11023390
    Abstract: Resizing circuitry comprises at least one buffer having buffer entries each corresponding to one of at least two shift registers, each shift register comprising storage circuits connected in a ring to transfer a token bit between storage circuits. Selection circuitry controls, based on the shift registers, writing of data sections of input data units having a first number of data sections to the buffer(s), to form output data units having a second number of data sections. For a given buffer entry corresponding to a given shift register, depending on whether the token bit is stored in a first or second subset of storage circuits, the selection circuitry controls writing of a selected data section of a received input data unit to the given buffer entry or prevents overwriting of the given buffer entry. At least two of the shift registers have different relative arrangements of the first and second subsets of storage circuits.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 1, 2021
    Assignee: Arm Limited
    Inventors: Eduard Vardanyan, Sean James Salisbury
  • Patent number: 11016763
    Abstract: Systems, apparatuses, and methods for compacting multiple groups of micro-operations into individual cache lines of a micro-operation cache are disclosed. A processor includes at least a decode unit and a micro-operation cache. When a new group of micro-operations is decoded and ready to be written to the micro-operation cache, the micro-operation cache determines which set is targeted by the new group of micro-operations. If there is a way in this set that can store the new group without evicting any existing group already stored in the way, then the new group is stored into the way with the existing group(s) of micro-operations. Metadata is then updated to indicate that the new group of micro-operations has been written to the way. Additionally, the micro-operation cache manages eviction and replacement policy at the granularity of micro-operation groups rather than at the granularity of cache lines.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: May 25, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jagadish B. Kotra, John Kalamatianos
  • Patent number: 10990393
    Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 27, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: John Kalamatianos, Krishnan V. Ramani, Susumu Mashimo
  • Patent number: 10990406
    Abstract: An instruction execution device includes a processor. The processor includes an instruction translator, a reorder buffer, an architecture register, and an execution unit. The instruction translator receives a macro-instruction and translates the macro-instruction into a first micro-instruction, a second micro-instruction and a third micro-instruction. The instruction translator marks the first micro-instruction and the second micro-instruction with the same atomic operation flag. The execution unit executes the first micro-instruction to generate a first execution result and to store the first execution result in a temporary register. The execution unit executes the second micro-instruction to generate a second execution result and to store the second execution result in the architecture register. The execution unit executes the third micro-instruction to read the first execution result from the temporary register and to store the first execution result in the architecture register.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 27, 2021
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Penghao Zou, Zhi Zhang
  • Patent number: 10983794
    Abstract: An processor to facilitate register sharing is disclosed. The processor includes a plurality of execution units (EUs), each including a General Purpose Register File (GRF) having a plurality of registers; and register sharing hardware to divide the plurality of registers into a first set of registers dedicated for execution of a first set of threads and a second set of registers shared for execution of a second set of threads.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Guei-Yuan Lueh, Subramaniam Maiyuran, Weiyu Chen, Konrad Trifunovic, Supratim Pal, Chandra S. Gurram, Jorge E. Parra, Pratik J. Ashar, Tomasz Bujewski
  • Patent number: 10983793
    Abstract: The present disclosure is directed to systems and methods of performing one or more broadcast or reduction operations using direct memory access (DMA) control circuitry. The DMA control circuitry executes a modified instruction set architecture (ISA) that facilitates the broadcast distribution of data to a plurality of destination addresses in system memory circuitry. The broadcast instruction may include broadcast of a single data value to each destination address. The broadcast instruction may include broadcast of a data array to each destination address. The DMA control circuitry may also execute a reduction instruction that facilitates the retrieval of data from a plurality of source addresses in system memory and performing one or more operations using the retrieved data. Since the DMA control circuitry, rather than the processor circuitry performs the broadcast and reduction operations, system speed and efficiency is beneficially enhanced.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Joshua Fryman, Ankit More, Jason Howard, Robert Pawlowski, Yigit Demir, Nick Pepperling, Fabrizio Petrini, Sriram Aananthakrishnan, Shaden Smith
  • Patent number: 10977038
    Abstract: A processing apparatus supporting register renaming is provided with checkpoint circuitry to capture register mapping checkpoints indicative of speculative register mappings between logical registers and physical registers at a given point of speculative execution, and register group tracking circuitry to maintain tracking information for groups of logical registers. The tracking information for a given group indicates whether the given group is a changed group comprising at least one logical register for which a corresponding speculative register mapping has changed since a last checkpoint was captured, or an unchanged group for which none of the logical registers in that group have had their speculative register mappings changed since the last checkpoint was captured. When capturing a new register mapping checkpoint, unchanged groups of logical registers are excluded from the new register mapping checkpoint. This can save power in a register mapping checkpointing scheme.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 13, 2021
    Assignee: Arm Limited
    Inventor: William Elton Burky