Abstract: Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand.

Abstract: Methods, systems, and devices for a data circuit for a low swing data bus are described. An apparatus may include a data bus that may transfer data at a first voltage different than a second voltage that is associated with one or more components of the memory array. A transistor, coupled with the data bus, may receive the second voltage and send a third voltage. A first in first out (FIFO), coupled with the transistor, may receive the third voltage from the transistor. The FIFO circuit may include one or more precharge components that drive an input voltage of the FIFO circuit to the second voltage associated with the one or more components of the memory array based on receiving the third voltage.

Abstract: Methods and systems are disclosed to monitor a media device via a universal serial bus (“USB”) port. An example method includes obtaining a voltage output by a UBS port of the media device and determining if the voltage exceeds a threshold. If the voltage exceeds the threshold, the example method includes determining the media device is in an on state. If the voltage does not exceed the threshold, the example method includes determining the media device is in an off state.

Abstract: Technology is disclosed herein for per pin internal reference voltage generation for data receivers in non-volatile memory systems. A receiving circuit may have an on-die voltage generator that has inputs to receive a separate voltage magnitude select signal for each data receiver on the receiving circuit. The on-die voltage generator provides a separate reference voltage for each data receiver. This allows the reference voltage for each data receiver to be calibrated separately. A separate reference voltage for each data receiver compensates for variations between data paths, and provides for a wider data valid window than if the same reference voltage were used for all data receivers. Generating the different reference voltages on-die can potentially require a large area, as well as consume considerable power and/or current. A voltage divider and multiplexers may provide the different reference voltages, which saves space and is power and current efficient.

Abstract: A system includes multiple memory-compute nodes coupled to one another over a scale fabric, where each memory-compute node includes a hybrid threading processor; a memory controller; a fabric interface; and a network on chip (NOC) that provides communication between the hybrid threading processor, the fabric interface, and the memory controller, wherein the fabric interface supports a first virtual channel (VC0), and a second virtual channel (VC1) to the NOC, and supports the first virtual channel (VC0), the second virtual channel (VC1), and a third virtual channel (VC2) to the scale fabric.

Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

Abstract: To provide a structure capable of more reliably completing a series of processes performed by a plurality of devices. There is provided a system comprising: a plurality of processing devices that execute a predetermined process according to an input process request, wherein each of the plurality of processing devices is connected to at least one other processing device such that information is transmittable, wherein the process request is input from an external device connected to any of the plurality of processing devices, and wherein each of the plurality of processing devices starts the predetermined process on the basis of, among the other processing devices, all processing devices receiving information from the external device via the processing device having completed the predetermined process normally.

Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

Abstract: An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.

Abstract: The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed in a host side to include: obtaining a value of an extended device-specific data (Ext_CSD) register in a flash controller from the flash controller, where the host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol; and allocating space in a system memory as an HPA buffer, and storing a plurality of first logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller when the value of the Ext_CSD register comprises information indicating that an HPA function is supported, where each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device.

Abstract: Examples relate to managing distribution of a total number of I/O queue pairs of an NVMe target among a plurality of NVM subsystems of the NVMe target and a plurality of hosts connected to the NVMe target. A target controller of the NVMe target defines a number of I/O queue pairs for a dedicated pool and a number of I/O queue pairs for a reserved pool based on the total number of I/O queue pairs. The target controller distributes a number of I/O queue pairs to each of the hosts from the number of I/O queue pairs of the dedicated pool and utilizes the number of I/O queue pairs of the reserved pool to balance out the number of I/O queue pairs on each of the hosts by selectively changing the number of I/O queue pairs of the reserved pool.

Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.

Abstract: A data transmission method for a convolution operation, and a convolution operation apparatus including a fetcher that includes a loader, at least one sender, a buffer controller, and a reuse buffer. The method includes loading, by the loader, input data of an input feature map according to a loading order, based on input data stored in the reuse buffer, a shape of a kernel to be used for a convolution operation, and two-dimensional (2D) zero-value information of weights of the kernel; storing, by the buffer controller, the loaded input data in the reuse buffer of an address cyclically assigned according to the loading order; and selecting, by each of the at least one sender, input data corresponding to each output data of a convolution operation among the input data stored in the reuse buffer, based on one-dimensional (1D) zero-value information of the weights, and outputting the selected input data.

Abstract: The present disclosure provides a computation method and product thereof. The computation method adopts a fusion method to perform machine learning computations. Technical effects of the present disclosure include fewer computations and less power consumption.

Abstract: Methods and apparatus for improved data movement operations through interconnect fabric. In one embodiment, Non-Transparent Bridge (NTB) technology used to perform data movement operations between a host and multiple peer devices using a DMA (direct memory access) engine and at least one descriptor ring having enhanced descriptor entries. In one implementation, descriptor ring entries include source and destination address information, address translation information, and fabric partition information. In one implementation, a DMA engine is configured directly access host memory and generate data packets using the descriptor entry information. In one embodiment, the descriptor ring is a virtual descriptor ring located on DMA hardware, host memory, or elsewhere in the NT fabric address space, and may be accessed by user processes.

Abstract: A memory controller includes an address decoder, a first command queue coupled to a first output of the address decoder for receiving memory access requests for a first memory channel, and the second command queue coupled to a second output of the address decoder for receiving memory access requests for a second memory channel. A request credit control circuit is coupled to the first command queue and the second command queue, and operates to track a number of outstanding request credits. The request credit control circuit issues a request credit in response to a designated event based on a number of available entries of the first and second command queues.

Abstract: Systems and methods are disclosed and include receiving, with a peripheral device, a message packet from a portable device, the message packet including an authenticated packet with a de-whitened tone byte inserted therein. The portable device generates first message authentication code (MAC) bytes based on a shared secret key and generates the authenticated packet based on the first MAC bytes, first nonce bytes, and a message byte. The peripheral device validates the message packet in response to determining that the first MAC bytes match second MAC bytes and that the first nonce bytes match second nonce bytes. The peripheral device generates a reconstructed message packet in response to validating the message packet by removing the de-whitened tone byte from the authenticated packet. The communication gateway establishes a communication link between the portable device and the communication gateway in response to receiving the reconstructed message packet.

Abstract: A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.

Abstract: Deferred command execution by a command processor (CP) may be performed based on a determination that at least one command of a primary buffer is located between a first link of the primary buffer and a second link of the primary buffer. The first link and the second link may be to one or more secondary buffers that includes a set of commands. The CP may initiate, before executing, a fetch of a first set of commands in the set of commands based on the first link, a fetch of the at least one command of the primary buffer, and a fetch of a second set of commands in the set of commands based on the second link. After initiating the fetch of the second set of commands, the CP may execute the first set of commands, the at least one command of the primary buffer, and the second set of commands.