Patents Examined by Michael Trinh
  • Patent number: 10170556
    Abstract: A semiconductor device manufacturing method includes preparing a semiconductor substrate of a first conductivity type, forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate, forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate, forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction, and covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 1, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Wataru Sumida, Akihiro Shimomura
  • Patent number: 10164218
    Abstract: Disclosed is a manufacturing apparatus of a light-emitting element including: a main transporting route extending in a first direction, the main transporting route comprising first and second transfer devices connected through a first transporting chamber; a sub-transporting route extending in a second direction intersecting the first direction, the sub-transporting route comprising a second transporting chamber connected to the first or second transfer device and a delivery chamber connected to the second transfer chamber; and a plurality of first treatment chambers connected to the delivery chamber. The main transporting route is configured to transfer a substrate to be treated in a horizontal state, and one of the plurality of treatment chambers is configured to hold the substrate in a vertical state during treatment.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 25, 2018
    Assignee: Japan Display Inc.
    Inventors: Takaaki Ishikawa, Takaaki Kamimura, Noriyuki Hirata
  • Patent number: 10158074
    Abstract: An organic layer deposition assembly for depositing a deposition material on a substrate includes a deposition source configured to spray the deposition material, a deposition source nozzle arranged in one side of the deposition source and including deposition source nozzles arranged in a first direction, a patterning slit sheet arranged to face the deposition source nozzle and having patterning slits in a second direction that crosses the first direction, and a correction sheet arranged between the deposition source nozzle and the patterning slit sheet and configured to block at least a part of the deposition material sprayed from the deposition source.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: December 18, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youngsun Cho, Daeyong Kim, Jongbum Kim, Jongho Yang, Yoonchan Oh
  • Patent number: 10157948
    Abstract: An image sensor includes a two-dimensional array of image sensor pixels, which are formed in a semiconductor layer. Each image sensor pixel is formed in a substrate having a corresponding semiconductor region therein. Each semiconductor region contains at least first and second photoelectric conversion elements, which are disposed at side-by-side locations therein. An electrically insulating isolation region is also provided, which extends at least partially through the semiconductor region and at least partially between the first and second photoelectric conversion elements, which may be configured respectively as first and second semiconductor regions of first conductivity type (e.g., N-type). At least one optically reflective region is also provided, which extends at least partially through the semiconductor region and surrounds at least a portion of at least one of the first and second photoelectric conversion elements. A semiconductor floating diffusion (FD) region (e.g.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: December 18, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungho Lee, Hyuk An, Hyuk Soon Choi
  • Patent number: 10141317
    Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 10134763
    Abstract: The capacitance between gate structures and source/drain contacts of FinFET devices is reduced by the incorporation of inner spacers in the top portions of the gate structures. A replacement metal gate process used in the fabrication of such devices includes formation of the inner spacers following partial removal of dummy gate material. The remaining dummy gate material is then removed and replaced with gate dielectric and metal gate material.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10134877
    Abstract: A method for manufacturing an organic light emitting diode (OLED) display can include forming a gate electrode on a substrate, forming a semiconductor layer by depositing a gate insulating layer and an oxide semiconductor material and patterning the oxide semiconductor material, forming an etch stopper on a central portion of the semiconductor layer, conducting a plasma treatment using the etch stopper as a mask to conductorize portions of the semiconductor layer exposed by the etch stopper for defining a channel area, a source area and a drain area, and forming a source electrode contacting portions of the conductorized source area and a drain electrode contacting portions of the conductorized drain area.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 20, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sungjin Hong, Byungchul Ahn, Youngju Koh, Woojin Nam, Ryosuke Tani
  • Patent number: 10121988
    Abstract: A flexible display apparatus includes a flexible display panel which includes a flexible display substrate having an active area and an inactive area outside the active area. The inactive area which extends from the active layer and includes a bending area foldable or adapted to be folded in a first direction. The bending area includes a deformation unit that includes a plurality of unit deformable portions such that the flexible display panel is foldable or adapted to be folded in a second direction. The flexible display substrate may include an encapsulation layer on the flexible display substrate. The flexible display apparatus may include a functional layer on a side of the flexible display panel. A folded end portion of the flexible display panel may be on the functional layer. The flexible display apparatus may also include a driving unit.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 6, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soohee Oh, Hyunggyu Park, Seonggeun Won, Hirotsugu Kishimoto
  • Patent number: 10115629
    Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas J. Haigh, Juntao Li, Eric G. Liniger, Sanjay C. Mehta, Son V. Nguyen, Chanro Park, Tenko Yamashita
  • Patent number: 10109484
    Abstract: Method for producing nanocrystals of semiconductor, comprising at least: ion bombardment of a thin layer of semiconductor arranged on at least one dielectric layer, achieving at least one among an implantation of ions of at least one chemical element of rare gas type and an implantation of ions of at least one semiconductor element of same nature as that of the thin layer, in at least one part of the thickness of the thin layer; annealing of the thin layer achieving a dewetting of the semiconductor of the thin layer and forming, on the dielectric layer, nanocrystals of semiconductor.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: October 23, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Yann Almadori, Jean-Charles Barbe, Lukasz Borowik
  • Patent number: 10103093
    Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: October 16, 2018
    Assignee: Invensas Corporation
    Inventors: Zhuowen Sun, Cyprian Emeka Uzoh, Yong Chen
  • Patent number: 10103322
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A hard mask layer is provided on the MTJ stack. The hard mask layer is patterned to form a hard mask. The MTJ stack is patterned to form a MTJ device wherein sidewall damage is formed on sidewalls of the MTJ device. The sidewall damage is removed by applying a CMP slurry which physically attacks and removes the sidewall damage on the MTJ device.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: October 16, 2018
    Assignee: Headway Technologies Inc.
    Inventors: Zhongjian Teng, Tom Zhong, Jesmin Haq
  • Patent number: 10090267
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a modified conductive pillar having a top portion and a bottom portion formed over the metal pad and a solder layer formed over the modified conductive pillar. In addition, the top portion of the modified conductive pillar has a first sidewall in a first direction and a bottom portion of the modified conductive pillar has a second sidewall in a second direction different from the first direction.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: October 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
  • Patent number: 10074784
    Abstract: In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: September 11, 2018
    Assignee: CRYSTAL IS, INC.
    Inventors: Leo J. Schowalter, Jianfeng Chen, James R. Grandusky
  • Patent number: 10062704
    Abstract: A method is provided for fabricating a buried-channel MOSFET and a surface-channel MOSFET of the same type and different gate electrodes on a same wafer. The method includes providing a semiconductor substrate having a well area and a plurality of shallow trench isolation structures; forming a threshold implantation region doped with impurity ions opposite of that of the well area in the well area for the buried-channel MOSFET; forming a gate structure including a gate dielectric layer and a gate electrode on the semiconductor substrate, wherein the gate electrode of the buried-channel MOSFET is doped with impurity ions with a same type as that of the well area, and the gate electrode of the surface-channel MOSFET is doped with impurity ions with a type opposite of that of the well area; and forming source and drain regions in the semiconductor substrate at both sides of the gate structure.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 28, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Tzu Yin Chiu, Clifford Ian Drowley, Leong Tee Koh, Yu Lei Jiang, Da Qiang Yu
  • Patent number: 10056388
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; performing a first ion implantation process to form a first doped region having a first conductive type in the substrate adjacent to the trench; forming a gate electrode in the trench; and performing a second ion implantation process to form a second doped region having a second conductive type in the substrate above the gate electrode.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: August 21, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ger-Pin Lin, Yung-Ming Wang, Tien-Chen Chan, Shu-Yen Chan
  • Patent number: 10052657
    Abstract: A method of manufacturing a film includes disposing a substrate under one side of a baffle plate in a film manufacturing space, the baffle plate having a plurality of through-holes, and spraying an inert gas toward the substrate through a plurality of nozzle tips branched from a gas distribution pipe that is disposed over an other side of the baffle plate such that the inert gas penetrates the baffle plate through the through-holes.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 21, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Katsushi Kishimoto
  • Patent number: 10056486
    Abstract: Methods to reduce a width of a channel region of Si fins and the resulting devices are disclosed. Embodiments include forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin; and forming a high-k/metal gate in the cavity.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shesh Mani Pandey, Pei Zhao, Zhenyu Hu
  • Patent number: 10050010
    Abstract: A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to form a masked putty pad. The masked putty pad has a first area that is exposed and a second area that is masked. The process also includes exposing the masked putty pad to UV light to form a selectively cross-linked putty pad. The process includes disposing the selectively cross-linked putty pad between an electrical component and a heat spreader to form an assembly. The process further includes compressing the assembly to form a thermal interface material structure that includes a selectively cross-linked thermal interface material.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Campbell, Sarah K. Czaplewski, Elin Labreck, Jennifer I. Porto
  • Patent number: 10050131
    Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.
    Type: Grant
    Filed: December 11, 2016
    Date of Patent: August 14, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Jack Wong, Sajid Kabeer, Mel Hymas, Santosh Murali, Brad Kopp