Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a barrier including carbon over a fin, the fin including a doped region. The semiconductor device includes an epitaxial (Epi) cap over the barrier, the Epi cap including phosphorus. The barrier inhibits phosphorus diffusion from the Epi cap into the fin as compared to a device that lacks such a barrier. The inhibition of the phosphorus diffusion reduces a short channel effect, thus improving the semiconductor device function.

Abstract: In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical MOSFET includes first ditches, second ditches, and gate electrodes. The first ditches are formed in an upper surface portion of an epitaxial layer formed over a semiconductor substrate and extend in a second direction extending along a main surface of the semiconductor substrate. The second ditches are formed in bottom surface portions of each of the first ditches and are arranged in the second direction. The gate electrodes are formed in the first ditches and second ditches. The gate electrodes formed in the first ditches include lower electrodes arranged in the second direction.

Abstract: This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier substrate; forming a first dielectric layer on the first carrier substrate while enabling an end face of the first connecting unit to be exposed; bonding a second carrier substrate to the first dielectric layer and removing the first carrier substrate; disposing a first circuit chip and a second connecting unit on the first conductive wire; forming a second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be surrounded by the second dielectric layer and an end face of the second connecting unit to be exposed; forming a second conductive wire on the second dielectric layer; disposing a second circuit chip on the second conductive wire; and forming a third dielectric layer on the second carrier substrate.

Abstract: There is provided an organic light emitting diode display including: a substrate having a pixel area and a surrounding area enclosing the pixel area; an OLED formed in the pixel area; an anti-overflowing groove formed in the surrounding area of the substrate; and a dam positioned between the anti-overflowing groove and an end of the substrate.

Abstract: A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method comprises forming an active fin extending along a first direction; forming a field insulating layer exposing an upper part of the active fin, along long sides of the active fin; forming a dummy gate pattern extending along a second direction intersecting the first direction, on the active fin; forming a spacer on at least one side of the dummy gate pattern; forming a liner layer covering the active fin exposed by the spacer and the dummy gate pattern; forming a dopant supply layer containing a dopant element, on the liner layer; and forming a doped region in the active fin along an upper surface of the active fin by heat-treating the dopant supply layer.

Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.

Abstract: A light-emitting device includes a substrate, a light-emitting element disposed on the substrate, and a sealing member for sealing the light-emitting element. The sealing member contains at least a particulate red phosphor. The red phosphor contains at least a Mn4+-activated fluoride complex phosphor. The sealing member has an upper surface with irregularities on at least part of the upper surface.

Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

Abstract: A light-emitting element layer and an element layer, which includes an anode and a cathode that sandwich the light-emitting element layer, are formed, and a sealing film is formed so as to cover the entire element layer. In the step of forming the sealing film, a first inorganic film is formed on the element layer. An organic film is formed on the first inorganic film. The organic film is ashed by using a foreign substance remaining on the organic film as a mask such that the organic film is left at least immediately below the mask and removed from at least a part of other areas. After the organic film is ashed, a second inorganic film is formed at least on the first inorganic film.

Abstract: A method of manufacturing an image sensor device includes providing a metalized thin film transistor layer on a glass substrate; forming an inter-layer dielectric layer on the metalized thin film transistor layer; forming a via through the inter-layer dielectric layer; forming a metal layer the inter-layer dielectric and within the inter-layer dielectric layer via for contacting the metalized thin film transistor layer; forming a bank layer on the metal layer and the inter-layer dielectric layer; forming a via through the bank layer; forming an electron transport layer on the bank layer and within the bank layer via for contacting an upper surface of the metal layer; forming a bulk heterojunction layer on the electron transport layer; forming a hole transport layer on the bulk heterojunction layer; and forming a top contact layer on the hole transport layer.

Abstract: A method of manufacturing an sensor array includes providing a glass substrate; forming a bottom electrode layer over the glass substrate; forming a sensor material layer over the bottom electrode layer; forming a top electrode layer over the sensor material layer; patterning the top electrode layer, the sensor material layer, and the bottom electrode layer using a first photoresist layer to form a plurality of pixels; detecting a defect in the plurality of pixels; and patterning the plurality of pixels using a second photoresist layer. The first photoresist layer includes a plurality of first pixel patterns and the second photoresist layer comprises a plurality of second pixel patterns, and wherein at least one of the second pixel patterns has an area greater than that of a corresponding first pixel pattern.

Abstract: A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

Abstract: An organic light-emitting display apparatus includes a substrate; a plurality of pixels disposed on the substrate, each of the plurality of pixels including a first region through which light is emitted and a second region through which external light is transmitted; a pixel circuit unit disposed in the first region of each of the plurality of pixels and including at least one thin-film transistor (TFT); a black matrix covering the pixel circuit unit and including a first opening corresponding to the second region; a via-insulating film disposed on the black matrix and including a second opening corresponding to the second region; and a light-emitting device disposed in the first region on the via-insulating film.

Abstract: In various embodiments, photovoltaic devices incorporate discontinuous passivation layers (i) disposed between a thin-film absorber layer and a partner layer, (ii) disposed between the partner layer and a front contact layer, and/or (iii) disposed between a back contact layer and the thin-film absorber layer.

Abstract: A method of manufacturing a semiconductor device, includes: supplying a first precursor and a first nitriding agent onto a substrate having a surface formed thereon with an oxygen-containing film in order to form an initial film on the oxygen-containing film; modifying the initial film into a first nitride film by nitriding the initial film with plasma; and supplying a second precursor and a second nitriding agent onto the substrate in order to form a second nitride film on the first nitride film.

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract: A method of manufacturing LED packages includes the steps of: forming a conductive circuit layer on a substrate; screen printing a wall layer on the conductive circuit layer to form a trellis with a plurality of wall units, so that regions of the conductive circuit layer surrounded by the wall units are exposed; mounting and electrically connecting at least one LED die on the conductive circuit layer within each of the wall units; molding a transparent layer to cover the LED dies; and cutting along the wall units to form a plurality of LED packages.

Abstract: A method of degassing semiconductor substrates includes sequentially loading a plurality of semiconductor substrates into a degas apparatus, and degassing the semiconductor substrates in parallel, the degassing of each semiconductor substrate commencing at a different time related to the time at which the semiconductor substrate was loaded into the degas apparatus. The method further includes unloading a semiconductor substrate from the degas apparatus when the semiconductor substrate has been degassed, while semiconductor substrates which were loaded later in the sequence are still being degassed. The degassing of the semiconductor substrates is performed at pressure of less than 10?4 Torr, and the degas apparatus is pumped continuously during the degassing of the semiconductor substrates.